Ranbir Singh

Software Engineer

Bengaluru, Karnataka, India4 yrs 11 mos experience

Key Highlights

Expert in advanced-node SoC implementation.
Proven track record of achieving timing closure.
Skilled in optimizing power, performance, and area.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in advanced-node physical design.

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Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Logic SynthesisFloorplanningPowerplanPlacementCTSRoutingMMMC analysisIR-drop analysisPrimeTimeRedhawkVoltusSDC constraintsECOsVery-Large-Scale Integration (VLSI)Unified Power Format (UPF)

About

As a Physical Design Engineer with over 4 years’ experience in advanced-node (7 nm/5 nm/3nm) SoC implementation in Synthesis, Physical Design (PD), and Static Timing Analysis (STA) — building efficient, high-performance chips at advanced technology nodes (7nm, 5nm, and below). Over the years, I’ve worked on multiple end-to-end projects, helping deliver low-power, high-speed silicon from RTL to GDSII. My expertise covers the entire physical implementation flow — from RTL synthesis, floorplanning, and power planning, to placement, CTS, routing, and final timing, power, and DRC signoff. I enjoy the challenge of balancing performance, power, and area, and I’m deeply skilled in MMMC analysis, timing constraints (SDC) development, and functional ECOs for both synthesis and STA. I’m proficient in industry-standard tools like Design Compiler, Genus, ICC2, Innovus, PrimeTime, Redhawk, and Voltus, and familiar with low-power UPF methodologies and IR-drop analysis. What drives me is the satisfaction of turning complex design challenges into optimized, production-ready silicon. I’m always looking to grow as an engineer and contribute to cutting-edge chip design and physical implementation teams pushing the boundaries of what’s possible.

Experience

4 yrs 11 mos

Total Experience

2 yrs 6 mos

Average Tenure

2 yrs 5 mos

Current Experience

Mediatek

Physical Design Engineer

Dec 2023 – Present · 2 yrs 5 mos · Bengaluru · On-site

Led the complete physical implementation flow from RTL to GDSII for multiple SoC blocks on 3nm and 5nm nodes, achieving timing closure within ±10ps of target and reducing design turnaround time by 15%.
Optimized power, performance, and area (PPA) through floorplanning, placement, CTS, and routing, delivering up to 8% area savings in high-frequency modules.
Collaborated closely with front-end and verification teams to resolve over 300+ timing and functional ECOs, ensuring clean signoff at tapeout.
Executed MMMC and IR-drop analysis using PrimeTime, RedHawk, and Voltus to ensure power integrity and robust design margins.
Contributed to the development of internal automation scripts, reducing repetitive tasks in signoff and ECO handling by 20%.
Key Achievements:
✔ Delivered multiple high-performance, low-power SoC blocks that successfully taped out on time.
✔ Recognized by project leads for consistently achieving aggressive timing closure targets.

Physical DesignStatic Timing AnalysisLogic SynthesisFloorplanningPowerplanPlacement+7

Cyient

Physical Design Engineer

Jun 2021 – Dec 2023 · 2 yrs 6 mos · Hyderabad · On-site

Executed physical design flows for 5nm and 7nm SoCs, handling floorplanning, placement, CTS, routing, and timing closure.
Improved block-level power efficiency by 10% through refined power grid design and early congestion analysis.
Developed and maintained SDC constraints and implemented ECOs, improving synthesis-to-layout correlation and reducing STA violations by 25%.
Supported multi-corner, multi-mode (MMMC) analysis and contributed to design signoff with zero timing and DRC violations.
Key Achievements:
✔ Played a key role in the successful tapeout of two large ASIC blocks for global semiconductor clients.
✔ Built strong foundations in physical implementation that enabled faster ramp-up at advanced nodes in later roles.

Physical DesignStatic Timing AnalysisLogic SynthesisFloorplanningPowerplanPlacement+5