Sourav Mishra

Software Engineer

Noida, Uttar Pradesh, India3 yrs 10 mos experience

Key Highlights

Two years of experience in memory design at Arm.
Expertise in memory subsystem optimization for semiconductors.
Proficient in industry-standard EDA tools and methodologies.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in memory systems and VLSI design.

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Skills

Core Skills

Digital Ic DesignCadence VirtuosoMemory DesignStatic Timing AnalysisBitcell AnalysisDebuggingVlsi DesignDigital Logic Design

Other Skills

AnalogCustom waveviewSynopsys XA/HSPICE SimulatorCadence SpectreSolido Design EnvironmentShellMonte Carlo SimulationsPDK ComparisonVoltage Noise AnalysisUnix/LinuxShell ScriptingIntroduction to VLSI DesignSystem VerilogVerilog HDLRadio Frequency Integrated Circuit (RFIC)

About

Electronics Engineer by passion , not by circumstances. Passionate memory design engineer with 2 years of experience at Arm, specializing in the development and optimization of memory subsystems for cutting-edge semiconductor products. Proficient in designing and implementing memory flows, including SRAMs, while ensuring high performance, low power consumption, and reliability. Skilled in using industry-standard EDA tools and methodologies to conduct design, verification, and validation processes. Collaborative team player with a strong analytical mindset and problem-solving skills, dedicated to delivering innovative solutions that meet or exceed customer requirements. Skills: - Memory Design and Margining - SRAM Design - EDA Tools (Cadence, Synopsys, Mentor Graphics) - Circuit Design and Simulation - Timing and Power Analysis - Scripting Languages ( Shell ) - Collaborative Problem-Solving - Communication and Teamwork TOOLS & TECHNOLOGIES : - Tools: Synopsys XA/HSPICE Simulator, Cadence Spectre, Cadence Virtuoso. - Scripting Language: Shell - Technology Nodes: 22nm FinFET,14nm FinFET, 12nm FinFET

Experience

3 yrs 10 mos

Total Experience

2 yrs 1 mo

Average Tenure

1 yr 8 mos

Current Experience

Qualcomm

Engineer ( Standard Cell IP )

Sep 2024 – Present · 1 yr 8 mos · Noida, Uttar Pradesh, India · Hybrid

Standard Cell Front-End Team
Development, Validation and Release of multiple standard cell libraries across advanced nodes like N2P , N3E and N4C.
Execution of Advanced QA flows including slew restrictions analysis , voltage scaling and statistical characterization using IRV ( Independent Random Variable ) techniques.
Flow Benchmarking and Regression Analysis

AnalogDigital IC DesignCadence Virtuoso

Arm

Memory Design Engineer

Jul 2022 – Sep 2024 · 2 yrs 2 mos · Noida, Uttar Pradesh, India · Hybrid

Part of Global Team in the organization which is responsible for all global and device check activities using PVT Variations for finding best sigma (yield) of the memory compiler.
Sound grasps of Bitcell Analysis focusing on parameters like Read Current, Flip Time, SNM, Weak Bitcell.
Understanding of Access Disturb Margin (ADM), IREAD and Write Margin (WRM) of a 6T SRAM Bitcell.
Understanding of Assist Design techniques and Methodologies and their feasibility.
Analysis of Different Peripherals used in Compiler Design, such as Level Shifter, Sense Amplifier by calculation of sense amplifier offsets.
Understanding of Monte Carlo Simulations and Solido benchmarking of single and dual port compilers.
Completed Simulator Calibration for multiple single and dual port compilers.
PDK comparison based on offsets and sigma qualification for the compilers.
Keeper Analysis done for RF2P compiler.
Currently working in TSMC 22nm bug fix of read disturb issue in which debugged and compared ncurve margin methodology with tsmc nicell methodology based on voltage noise source.
TOOLS & TECHNOLOGIES
Tools: Synopsys XA/HSPICE Simulator, Cadence Spectre, Cadence Virtuoso , Solido Design Environment.
Scripting Language: Shell
Technology Nodes: 22nm FinFET, 14nm FinFET, 12nm FinFET

Static Timing AnalysisCustom waveviewSynopsys XA/HSPICE SimulatorCadence SpectreCadence VirtuosoSolido Design Environment+2

Exiger technologies

Graduate Design Engineer

Jul 2022 – Aug 2024 · 2 yrs 1 mo · Noida, Uttar Pradesh, India · Hybrid

Unix/LinuxShell Scripting

Maven silicon

Internship Trainee

Jul 2021 – Sep 2021 · 2 mos · Greater Noida · Remote

Dynamic and results-driven intern with hands-on experience in VLSI SoC design utilizing Verilog HDL. Contributed to the development of System-on-Chip (SoC) designs, implementing and verifying digital logic circuits. Applied knowledge of RTL design, synthesis, and timing analysis to optimize circuit performance.Eager to leverage skills and continue learning in the field of semiconductor design.

Introduction to VLSI DesignSystem VerilogVLSI Design