Achyut Mathad

Software Engineer

Karnataka, India2 yrs 10 mos experience

Highly Stable

Key Highlights

Expert in physical design from RTL to GDSII.
Hands-on experience with leading-edge nodes.
Proficient in industry-standard tools and scripting.

Stackforce AI infers this person is a VLSI design engineer with expertise in semiconductor technologies.

Contact

Skills

Core Skills

Physical DesignStatic Timing AnalysisMulti Voltage Design

Other Skills

Floor planningPlace and RouteDRC/LVSMachine learningpython scriptingRTL to gate level netlist generationSynthesisPlacementClock tree synthesisRoute flowsScriptingStrategic ThinkingUMC designUnified memory controllerPrimetime

About

Physical Design Engineer with a Master’s in Digital Electronics and Communication Engineering from Manipal Institute of Technology, and a Bachelor’s in Electronics and Communication Engineering from SDMCET, Dharwad. Currently working at AMD as a Silicon Design Engineer 2, I have hands-on experience in physical design implementation from RTL to GDSII — with a strong focus on Floorplanning, Placement, Routing, Congestion Analysis, STA, DRC, LVS, and Signoff. I’ve worked on leading-edge nodes, including N6 multi-voltage designs during my internship, and am currently engaged with UMC technologies. I’m proficient with industry-standard tools like Synopsys Fusion Compiler and PrimeTime, and have a solid understanding of PnR flows and timing closure methodologies. My skill set also includes scripting and automation using TCL, Perl, and Shell, with working knowledge of C, Python, MATLAB, and Verilog. I’m passionate about solving complex VLSI design challenges and contributing to innovative silicon solutions in the semiconductor industry.

Experience

2 yrs 10 mos

Total Experience

2 yrs 10 mos

Average Tenure

2 yrs 10 mos

Current Experience

Amd

2 roles

Silicon design engineer 2

Jul 2023 – Present · 2 yrs 10 mos

Floor planning
Place and Route
DRC/LVS
Machine learning
python scripting

Static Timing AnalysisPhysical DesignFloor planningPlace and RouteDRC/LVSMachine learning+1

Intern

Aug 2022 – Jul 2023 · 11 mos

RTL to gate level netlist generation through synthesis, placement, clock tree synthesis and route flows
Scripting to automate tasks and improve debug efficiency

Multi voltage designStatic Timing AnalysisRTL to gate level netlist generationSynthesisPlacementClock tree synthesis+2