sunil budumuru

DevOps Engineer

Hyderabad, Telangana, India20 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in DFT and VLSI methodologies.
  • Proven track record in low-power design.
  • Extensive experience in ATPG and MBIST implementations.
Stackforce AI infers this person is a DFT expert in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

DftVlsiAtpgMbistLow Power DftSynthesisTiming Analysis

Other Skills

Static Timing AnalysisLogic SynthesisDRCEDASoCLow-power DesignJTAGBISTSemiconductorsPhysical DesignRTL designSystemVerilogFunctional VerificationTiming ClosureTiming Simulations

Experience

20 yrs 7 mos
Total Experience
2 yrs 11 mos
Average Tenure
5 yrs 9 mos
Current Experience

Intel corporation

DFT Lead

Jul 2020 – Present · 5 yrs 9 mos · Hyderabad, Telangana, India

DFTStatic Timing AnalysisVLSILogic SynthesisATPGDRC+11

Dfx consultant - facebook

2 roles

Senior Design Engineer

Jun 2019 – Jul 2020 · 1 yr 1 mo

Senior Design Engineer

Sep 2014 – Jun 2019 · 4 yrs 9 mos

  • DFX - Test Architecture implementation / ATPG / Timing Simulations / MBIST / USB & MIPI DFT verification / Tester Support
ATPGTiming SimulationsMBISTUSB & MIPI DFT verificationTester SupportDFT

Dft consultant - qualcomm

2 roles

Senior Member Technical Staff (DFT)

Mar 2013 – Aug 2014 · 1 yr 5 mos

  • MBIST logic implementation / MBIST simulation bring up / BIST simulation Failure debug Analysis / ATPG & patterns validation.
MBIST logic implementationMBIST simulation bring upBIST simulation Failure debug AnalysisATPG & patterns validationMBISTATPG

Member Technical Staff

Jan 2012 – Mar 2013 · 1 yr 2 mos

  • Low power DFT, Smartscan test architecture design & implementation for a low pin ARM based micro controller. ATPG for stuck-at, transition fault models, Power component (Isolation cells, Retention cells & Power switch) testing. ATPG and pattern validations.
Low power DFTSmartscan test architecture designATPG for stuck-attransition fault modelsPower component testingATPG

Dft consultant - st microelectronics & infineon technologies

Technical Lead - DFT

Jun 2010 – Jan 2012 · 1 yr 7 mos · Hyderabad Area, India

  • Technical Lead - DFT Group
  • Synthesis / DFT logic implementation / Test coverage improvement implementations / Stuck-at & Transition fault model pattern generations and validation / Formal verification / Scan timing analysis
SynthesisDFT logic implementationTest coverage improvementFormal verificationScan timing analysisDFT

Ip core solutions (india) pvt. ltd (previously qualcore logic ltd)

SMTS (DFT/STA/Synthesis as Major Activities)

Feb 2010 – Jun 2010 · 4 mos · Hyderabad Area, India

  • Scan architecture development and implementation (DFT).
  • Scan pattern generation and validation.
  • Technology conversion projects.
  • Microsemi (aka Actel) back-end tool development and validation activities
  • Synthesis & Formal verification tasks
Scan architecture developmentScan pattern generationTechnology conversion projectsSynthesisFormal verificationDFT

Qualcore logic

SMTS (DFT/STA/Synthesis as Major Activities)

Dec 2005 – Jan 2010 · 4 yrs 1 mo · Hyderabad Area, India

  • Scan architecture development and implementation (DFT).
  • Scan pattern generation and validation.
  • Technology conversion projects.
  • Microsemi (aka Actel) back-end tool development and validation activities
  • Synthesis & Formal verification tasks
Scan architecture developmentScan pattern generationTechnology conversion projectsSynthesisFormal verificationDFT

Bit mapper integration technologies pvt. ltd.

Design Engineer

Jun 2005 – Nov 2005 · 5 mos

  • Design and Timing Analysis as major role
DesignTiming Analysis

Education

Motilal Nehru National Institute Of Technology

M.Tech — power electronics and asic design

Jan 2003 – Jan 2005

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