Abhishek Patel — Software Engineer
Stackforce AI infers this person is a VLSI Design Engineer with expertise in RTL verification and static timing analysis.
Location: Thanesar, Haryana, India
Experience: 2 yrs 3 mos
Skills
- Rtl Design
- Static Timing Analysis
Career Highlights
- Experienced in RTL design and verification.
- Strong background in VLSI design methodologies.
- Proven leadership as a placement coordinator.
Work Experience
Intel Corporation
SoC Design Engineer (10 mos)
Graduate Technical Intern (1 yr)
Training and Placement Cell, NIT Kurukshetra
Placement Coordinator (1 yr 5 mos)
Crisp
VLSI design (1 mo)
Education
Master of Technology - MTech at National Institute of Technology, Kurukshetra, Haryana
Bachelor of Technology - BTech at Rewa Engineering College, Rewa
12th at DAV PUBLIC school Nigahi
High school 10th at Kendriya Vidyalaya
Master of Technology - MTech at National Institute of Technology, Kurukshetra, Haryana
