Chetan Doddamani

Software Engineer

Bengaluru, Karnataka, India14 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and ASIC methodologies.
Proven track record in TSMC Physical Design Implementation.
Strong background in algorithm development for radar systems.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in ASIC methodologies.

Contact

Skills

Core Skills

Physical DesignAsic DesignAlgorithm Implementation

Other Skills

VLSIStatic Timing AnalysisUnixTSMC-28nm16nm Physical Design ImplementationFloor planningPlacementClock Tree SynthesisRoutingPhysical VerificationCMATLABPerlTCLCadence Encounter

About

Extensive experience in the field of physical implementation ( physical design) TECHNICAL SKILLS Programming Languages: C, Verilog . Scripting Languages: Perl,TCL. Programming Tools: ICC2,ICC, Cadence-Encounter,Primetime,Mentor Calibre.

Experience

14 yrs 5 mos

Total Experience

2 yrs 3 mos

Average Tenure

7 yrs 5 mos

Current Experience

Intel corporation

CPU Physical Design Engineer

Dec 2018 – Present · 7 yrs 5 mos · Bangalore Urban, Karnataka, India

VLSIASIC DesignPhysical DesignStatic Timing AnalysisUnix

Qualcomm

Senior Physical Design Engineer

Apr 2017 – Dec 2018 · 1 yr 8 mos · Bengaluru, Karnataka, India

Mediatek

Physical Design Engineer

Jul 2015 – Mar 2017 · 1 yr 8 mos · Bengaluru, Karnataka, India

Synapse design inc.

Physical Design Engineer

Jan 2015 – Mar 2017 · 2 yrs 2 mos · Bengaluru Area, India

TSMC-28nm and 16nm Physical Design Implementation of a block
The implementation of block from Netlist to GDSII.
Optimal placement of macros and Placement optimization iterations.
The design is timing critical and congested.
Responsible from Floor planning, Placement, Clock Tree Synthesis and Routing.
Physical Verification concepts (DRC, LVS and ANTENNA).

TSMC-28nm16nm Physical Design ImplementationFloor planningPlacementClock Tree SynthesisRouting+3

Broadcom

Intern

Jul 2013 – Jul 2014 · 1 yr · Bengaluru Area, India

Infosys technologies ltd

System Engineer

Aug 2010 – Jun 2012 · 1 yr 10 mos · Mangalore Area, India

Drdo, bangalore

Intern

Feb 2010 – Jun 2010 · 4 mos · Bangalore

The Project "Analysis of Constant False Alarm Rate Techniques" was carried out at the Electronics and Radar Development Establishment (LRDE), DRDO.
It aimed at reducing false alarms in radar receiver systems by using a efficient algorithm.Extensive study and implementation of algorithms using C and MATLAB.