Sushant Khobragade

Product Engineer

India15 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Digital IC Design and VLSI.
Proven track record in RTL design and verification.
Strong background in protocol development and optimization.

Stackforce AI infers this person is a Digital IC Design expert with a focus on VLSI and protocol development.

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Skills

Core Skills

Rtl DesignProtocol DevelopmentIp Design

Other Skills

Power Management Bus ProtocolStorage Bus ProtocolsHigh Speed Bus ProtocolVideo Bus ProtocolsSystem Bus ProtocolsRTL codinglintsynthesisCDC analysisdebugverification coverage improvementRTL Front-End Design FlowIP analysisMicroarchitecture designSimulation

About

• IIT Madras post graduate in “Microelectronics and VLSI Design” with years of experience in Digital IC Design • Skilled in Microarchitectural Specifications, RTL Design, Simulation, Functional Verification, Test Bench, FPGA Prototyping, Lint Checks, CDC Analysis and Synthesis • Delivered credible work in IP Design and Enhancement, RTL Front-End Design Flow, Hardware and Timing Optimization • Skilled in preparing technical documents through Visio, Architectural Block Diagrams, State Diagrams and Flow Charts

Experience

15 yrs 8 mos

Total Experience

3 yrs 11 mos

Average Tenure

5 yrs 5 mos

Current Experience

Infineon technologies

Principal Engineer

Dec 2020 – Present · 5 yrs 5 mos · India

Qualcomm

Senior Lead Engineer

Feb 2016 – Dec 2020 · 4 yrs 10 mos · Bengaluru Area, India

Protocols Experience:
Power Management Bus Protocol: SPMI
Storage Bus Protocols: SD, SDIO and EMMC
High Speed Bus Protocol: PCIe
Video Bus Protocols: DP and CVBS
System Bus Protocols: AHB, AXI, APB and ATB
Understand Standard Specifications/feature requirements and derive the functional specifications for the product and its features
Develop the architecture, create micro-architecture and detailed design documents of the design keeping in mind low power, area requirements
Individual contributor in the Design Tasks – RTL coding of design, lint, synthesis, CDC analysis, debug, verification coverage improvement in directed verilog test environment
Worked on control path oriented designs and asynchronous multiple clock designs.
Experience in quality processes (uflow) in the context of IP design
Logic and hardware optimization, pipelining and timing optimization in RTL for higher speed

Power Management Bus ProtocolStorage Bus ProtocolsHigh Speed Bus ProtocolVideo Bus ProtocolsSystem Bus ProtocolsRTL coding+7

Marvell india pvt ltd

Senior Digital IC Design Engineer

Jul 2011 – Jan 2016 · 4 yrs 6 mos · Bangalore

Experience On RTL Front-End Design Flow
o IP analysis from specification documents
o Microarchitecture design and hardware specification
o RTL design according to IP specification document
o C behavior model analysis, simulation and golden test vectors generation for RTL design verification
o C behavior model to equivalent verilog RTL design
o MDL behavioral model to equivalent verilog RTL design
o DSP and functionality analysis by reverse engineering RTL design
o Lint checks for RTL design using Spyglass and VCS lint tool
o CDC analysis using Spyglass tool
o RTL design synthesis and report analysis
o Logic and hardware optimization, pipelining and timing optimization in RTL for higher speed
o FPGA prototyping, Chipscope ILA design debug, design validation and real time evaluation
o Post silicon system validation, chip bring-up, signal probe and behavior analysis using Oscilloscope
o Test bench design and functional verification
o Design documentation
o On-site customer support
SKILLS SET
CDC Analysis Tool: Spyglass & 0in • Behavioral Modeling Tools: Verilog, Matlab, MDL, LT Spice & C
Linting Tools: VCS and Spyglass
Synthesis: dc shell • HDL Simulator Tool: VCS
Technical Document: Visio, flow chart, state & block diagram
Scripting: Shell script • RTL Debug and Analysis Tools: VCS, Verdi & Chipscope ILA
OS Tools: Unix & Linux