Vishal Jain

Software Engineer

Noida, Uttar Pradesh, India26 yrs 6 mos experience

Highly Stable

Key Highlights

Over 10 years of verification management experience.
Expert in SOC verification methodologies and DFT processes.
Proven leadership in managing engineering teams and projects.

Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in SOC and DFT methodologies.

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Skills

Core Skills

LeadershipVerificationManagementVerification ManagementArchitecture AnalysisSoc VerificationDft ManagementIp Development

Other Skills

IP Quality checksRTL integrationFormal VerificationTransaction Level ModelVerification platformFront End FlowUVM VerificationDFT flowDFT methodologiesIP DesignDebuggingRTL DesignEDAFunctional VerificationVerilog

About

Comprehensive problem solving abilities, excellent verbal and written communication skills, Experience Summary: - 3+ Years in field of CAD methodology for Subsystem and SOC integration using IP-XACT flow. Internal tool is used to generate XML and external tool is used to RTL Assembly. SOC lint and CDC checks are also performed before Synthesis for early bug detection. Worked on IP/SOC verification using constraint random testing based UVM methodology, Low power Verification using CPF/UPF, - 3+ Years in DFT team lead worked on DFT flow like scan insertion, Automatic Test pattern Generation, DFT functional and ATPG verification and its delivery for wafer testing. -10+ Years in Verification. I was responsible for SOC verification management activity includes planning, resource management, execution flow step and co-ordination with designers and verification team. - Hand on experience on Synthesis, Equivalence Check, Static Timing Analysis, Power estimation for IP or subsystem quality checks for early estimation of various parameters of SOC design like Area, Timing and Power for selected technology.

Experience

26 yrs 6 mos

Total Experience

3 yrs 11 mos

Average Tenure

3 yrs

Current Experience

Nxp semiconductors

Senior Principal Engineer

May 2023 – Present · 3 yrs · Noida, Uttar Pradesh, India · On-site

Stmicroelectronics

Group Manager

Jun 2018 – May 2023 · 4 yrs 11 mos · Greater Noida, Uttar Pradesh, India · On-site

Leadership

Incise infotech private limited

Director of engineering and Verification Consultant (Intel)

Jun 2017 – May 2018 · 11 mos · Noida

Managing Design and Verification team for ODC project. It includes managing IP Quality checks (Lint/CDC/UPF Checks), Synthesis and Timing Analysis, IP Verification, RTL integration for SOC, Subsystem and SOC Verification, Integration of internal and 3-party VIP.

Intel corporation

Senior Member Of Technical Staff, SOC Verification

Dec 2015 – Feb 2017 · 1 yr 2 mos · Malaysia

Working as Senior MTS SOC Verification, mainly involved in Subsystem and SOC verification activity planning, management and its execution. Responsible of deployment of best verification methodologies like formal verification to reduce the verification overall time cycle.

Stmicroelectronics pvt. ltd. india

5 roles

Senior Staff Engineer

Dec 2014 – Dec 2015 · 1 yr · Noida Area, India

Working with System Platform Group for delivering Transaction Level Model and Verification platform for architecture analysis and Firmware development.

Senior Staff Engineer

Dec 2010 – Nov 2014 · 3 yrs 11 mos · Noida Area, India

Working with Imaging Methodology team to develop Front End Flow, UVM based Verification and SOC Verification of Image Sensor and Co-processor.

Section Manager-DFT

Jan 2007 – Dec 2009 · 2 yrs 11 mos · Noida Area, India

Responsible for building and managing DFT team in GNOIDA site for processor and sensor activity.
Deployment of DFT flow in GNOIDA as it is used in other site. Support in development of new DFT methodology like Serial pattern generation for Low-pin count DFT especially for sensor.
Writing DFT Specification, RTL, Verification plan, test cases for sensor project.
Addition of DFT model like JTAG/SERDES in functional verification Environment to make to use the same in DFT functional test cases.
Support to Singapore Imaging design site for DFT functional and ATPG testing.

Senior Design & Verificaiton Engineer

Promoted

Feb 2005 – Nov 2006 · 1 yr 9 mos · Noida Area, India

Responsible for Managing Verification team for Imaging Co-processor.in support with Verification manager in Grenoble.
Responsible for writing Verification plan from functional specification. Task scheduling as per project schedule need.
Management of verification database, bugs, regression suite and status reporting to project management.

Design & Verificaiton Engineer

Feb 1998 – Jan 2005 · 6 yrs 11 mos · Noida Area, India

Responsible for IP design and its verification like DMA.
Development of south bridge subsystem includes various IPs like DMA, Keyboard controller, Interrupt controller.
Integration of PCI-ISA, PCI-LAN-PCI-USB, PCI-IRDA to make PCI subsystem using make scripts.