Maulin Sheth — Software Engineer

Experience in Scan insertion using Synopsys DFT-Compiler and Formal Verification using Synopsys Formality. Experience in ATPG (Stuck-At and TDT) using Synopsys TetraMAX. Worked on Test Coverage improvement, Low Power ATPG. Experience on Scan and Functional IP test pattern with and w/o timing Validation using VCS and NC-Verilog. Good knowledge of Perl Scripting and Makefile based flow creation. Hands on debugging experience using DVE and Verdi. Knowledge on Advanced Fault Models like Path Delat, Bridging, SDD Knowledge of Scan Compression, JTAG, IEEE1500 architecture. Skill Set : HDL : Verilog Synopsys Tools : DFT-Compiler, TetraMAX, Formality, VCS. Cadence : NC-Verilog , Sim-vision Scripting : Perl Goals: - Keep Learning. Strengthen Ability To View Future. - To enhance and keep Working Environment Sound And Motivating. - To be a significant contributor In the team.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in DFT and formal verification.

Location: Bengaluru, Karnataka, India

Experience: 15 yrs 3 mos