Anudeep J — Software Engineer

Design Verification Engineer with experience in working on IPs and Subsystems. . Currently working in CPU subsystem handling Debug, Trace & Analytics(DTA), Scandump on Post DFT Rtl and Low Power feature verification. • Developed Verification environments, Test Frame Works, Assertions and Automation tools from Scratch • Skilled in leading, Task planning and management, strategizing. • Experienced in Defining Verification strategies, Test-planning to Coverage, Regression closure. • Good at Problem Solving, Active learner and a Team Player. • Delivered first pass success in Silicon for below roles at Google, Xilinx, AMD and Siliconch Systems: - Low power verification of DSP processor Subsystems. - Gate Level Simulations of DSP processor Subsystems. - Verifying of Common PHY IP for Xilinx FPGAs in which extensively worked on DDR traffic support. - .Verification of Convolutional Neural Network(CNN) IP for Radeon Graphics SoC. - Verification of USB Power Delivery protocol from Scratch and testing the real time scenarios along with TYPE-C protocol - Experienced in Developing DDR VIPs. Skillset: System Verilog, Verilog, VHDL, UVM, Perl, Python, Ruby, C, OOPS, Functional and Code Coverage Analysis, Assertions, Low Power Verification, Gate level Simulations, Formal Verification - Beginner Protocols: I2C, UART, AMBA Protocols (APB, AXI, ACE, ATB, AXI-Stream), SPI, MESI(Cache), USBPD, Common PHY(DDR)

Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in low power and performance verification.

Location: Bengaluru, Karnataka, India

Experience: 12 yrs 8 mos