Apr 2019 – Dec 2024 · 5 yrs 8 mos · Toronto, Canada Area

• Programmable IP Engineering Team

Apr 2018 – Aug 2018 · 4 mos · Ottawa, Canada Area

• Digital PLLs in IDT's high-end Frequency Synthesizers
• System level scenarios involving various complex blocks like digital filters, PI loop controller, SDM/MMD based fractional dividers, digital phase/frequency detectors.

Sep 2017 – Apr 2019 · 1 yr 7 mos · Toronto, Canada Area

Nov 2016 – Jul 2017 · 8 mos

• Core IP Verification -----
• Bus Interconnect (High-speed Multi-Master Multi-Slave Heterogeneous design which is frontend to a DRAM Controller)
• Cache Controller (Set Associative with advanced and complex QoS Schemes)

Nov 2014 – Oct 2016 · 1 yr 11 mos

• Core IPs -----
• Protocol Bridge design (Multi-Master)
• Bus Interconnect (High-speed Multi-Master Multi-Slave Heterogeneous design which is frontend to a DRAM Controller)
• Cache Controller (Set Associative with advanced and complex QoS Schemes)
• Design complexity -----
• multiple QoS features, Burst breaking, Request and Response Ordering and very aggressive clock gating schemes.
• Data and protocol conversion internally across different master/slave combinations.
• Support for Multiple Caching Schemes, Multiple Cache Size, Complex Cache Maintenance Operations, Security and Sub-caching and exclusive fast channels.
• Quality Signoff -----
• Starting from Testplan Development, OVM/UVM-based VIP Development, complex OVM/UVM-based Checkers for all features, Assertion-based Verification, Formal Verification, Functional/Code Coverage (coding, analysis and closure), Regression maintenance
• Multiple configuration support -----
• Verification effort directed at developing infrastructure with ability to support multiple configurations in parallel
• Bug-free Design Delivery -----
• Numerous configurations of core designs proven in silicon over multiple Snapdragon SoCs with zero bugs till date
• Extensive knowledge of Protocols -----
• BUS Protocols (AMBA AXI, AMBA AHB and Qualcomm's in-house protocols)
• NOC Protocols (QNSx, NTTPx)

Jul 2013 – Oct 2014 · 1 yr 3 mos

• Worked on Verification of High-speed Multi-Master Multi-Slave Heterogeneous Bus Interconnect design
• OVM/UVM-based VIP Development, OVM/UVM-based Checkers and finally regression closing.

Jun 2012 – Aug 2012 · 2 mos · Bengaluru Area, India

• Designed UVM-based and highly scalable generic bus adapters in System Verilog to verify all data-width conversion across any widths from 32b to 1024b

Jun 2011 – Aug 2011 · 2 mos · New Delhi

• Electronic Circuit Designing, Manufacturing, Quality Control (Testing and Calibration) of High Voltage RF Medical Instruments like as Electrosurgical and Diathermy Units