Sri Charan

Software Engineer

Bengaluru, Karnataka, India2 yrs 9 mos experience

Key Highlights

  • Expert in RTL design and advanced bus protocols.
  • Strong background in digital design and verification.
  • Master's thesis on actuator design for drug delivery.
Stackforce AI infers this person is a Digital Design Engineer with expertise in ASIC and RTL design in the semiconductor industry.

Contact

Skills

Core Skills

Rtl DesignDigital DesignDesign Verification

Other Skills

VHDLStatic Timing AnalysisRegression AnalysisUniversal Verification Methodology (UVM)Telecommunications SystemsMIMOWireless Communications SystemsVLSI signal processingSpyglassVerdiAPBDebuggingDigital LogicArchitectural DesignAnalog Circuits

About

As a Senior Design Engineer at MediaTek, Bangalore, I specialize in RTL design, advanced bus protocols (APB, AXI), and managing IP to subsys integration. With a Master’s degree from IIT Kharagpur and extensive experience in digital design, I excel in creating efficient, reliable solutions for complex challenges. My journey includes a transformative VLSI Summer School and a Master's Thesis on 'Actuator Design for Drug Delivery Device,' both at IIT Kharagpur. Additionally, I gained practical industry experience during my internship at Texas Instruments, Bangalore, where I honed my skills in design verification. At MediaTek, I ensure high-quality designs through rigorous IP QC checks and collaboration with backend teams. My expertise includes CDC and Lint-friendly RTL designs, bus protocol integration. My commitment to innovation and continuous learning drives my success in enhancing system performance and reliability. Let’s connect to share insights and explore opportunities in digital design and engineering.

Experience

2 yrs 9 mos
Total Experience
1 yr 11 mos
Average Tenure
10 mos
Current Experience

Meta

ASIC Design Engineer

Jul 2025Present · 10 mos · Bengaluru, Karnataka, India · Hybrid

Mediatek

Senior RTL Design Engineer

Jul 2023Jun 2025 · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

VHDLStatic Timing AnalysisRTL DesignDigital Design

Texas instruments

Digital Design Engineer

May 2022Jul 2022 · 2 mos · Bengaluru, Karnataka, India

  • Enhanced and optimised regression experience for DV team.
Regression AnalysisUniversal Verification Methodology (UVM)Design VerificationDigital Design

Education

IIT Kharagpur

dual degree

Jul 2018May 2023

Indian Institute of Technology, Kharagpur

Embedded Wireless Systems — Telecommunications Engineering

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