Mayank Jain — Product Engineer

STA & Synthesis Engineer | Timing Closure | OCV/AOCV/POCV/SOCV | Tempus | PrimeTime | Genus | Fusion Compiler. Timing-driven VLSI engineer with hands-on experience in STA and RTL-to-Gate Synthesis for SoC designs. Skilled in setup/hold closure, timing ECOs, and deep analysis across OCV, AOCV, POCV, and SOCV methodologies. Exposure to logical and physical synthesis, timing-aware optimization, and cross-stage correlation between synthesis, STA, and physical implementation. Experienced in analyzing critical paths, fixing violations through cell sizing, buffering, logic restructuring, and collaborating closely with PnR teams for timing closure.

Stackforce AI infers this person is a VLSI engineering specialist with expertise in timing analysis and synthesis methodologies.

Location: Noida, Uttar Pradesh, India

Experience: 4 yrs