Aug 2012 – Sep 2014 · 2 yrs 1 mo · Bangalore

• Verification of memory PHY for AMD next generation APU and GPU.
• Domain expertise and Verification IP development of USB3.0
• Domain expertise and verification of DDR3,DDR4,GDDR6 PHY's for Tablets and Laptops
• Verification of GDDR6 PHY. Developed all verification components in UVM.
• HDL : Verilog, VHDL
• HVL: System Verilog
• Methodology : OVM/UVM/VMM,
• Debugging complex design issues.
• Perl
• Test plan development
• In house Verification methodolgy for AMD complex chips
• Tools:
• NCSIM, VCS, Questasim

Jul 2011 – Aug 2012 · 1 yr 1 mo · Bangalore

• Worked in Intel (Infosys) for new graphics technology
• Involved in Test Content Improvement of Intel’s New graphics chip. Work involved fault grading for different blocks of graphics chip.
• Responsibilities:
• Test debugging and correction.
• Debugging issues related to RTL and verification env.
• Handling Regression and fault grading tests.

Aug 2010 – Jun 2011 · 10 mos · Bengaluru, Karnataka, India

• SuperSpeed USB3.0 includes SuperSpeed USB Host, USB Device, Protocol Monitor and a Protocol Checker.
• Responsibilities:
• Development and verification of additional VIP features and development of the SuperSpeed USB 3.0 test suite:
• Developed additional features for USB3.0 Host and Device VIP in SystemVerilog like link LFPS features and LTSSM features.
• Developed OVM transactor, driver and sequences for USB3.0 OVM.
• Developed additional test suites for Host and device VIP in SystemVerilog.
• Writing test cases for Link Management and LTSSM features.
• Development of additional knobs in the BFM for configuration.
• USB3.0 Bug fixing

Mar 2008 – Sep 2010 · 2 yrs 6 mos · Noida, Uttar Pradesh, India

• IDesignSpec (IDS) is an engineering tool that allows a chip or system designer to create the design specification(using editor) once and automatically generate all possible views from it (verilog, vhdl, VMM RAL, OVM register definition, system RDL, IP-XACT1.4 and 1.5), without re-write or any duplication.
• Responsibilities:
• Representing System on chip (SOC) specification in XML.
• Convert design specification which is in the form of configurable registers into synthesizable VHDL and Verilog code.
• Generate automatically VHDL and verilog code using XML which is generated by the tool according to the information provided by chip designer. XSLT is used for conversion.
• Generate automatically SystemRDL, IP-XACT1.5 and VMM RAL from XML using XSLT.
• Generate OVM based register file automatically for the design (VHDL and verilog) to verify the design.
• Develop algorithms to calculate the addresses of registers automatically in the specification documents itself.
• Convert IP-XACT 1.4 and 1.5 back to the specification document.
• Include different register checks (like offset overlap, address location, duplicate register names etc) in the specification document itself.
• Develop verilog AMBA AHB transactors to talk with the automated design.
• Automatic Test bench generation in verilog to check the functionality of the automated design.
• Writing directed and random tests.
• Analyze different code coverage and functional coverage.
• Prepare user guide and documentation related to tools.
• Investigate new features and try to embed it into tool functionality according to customer requirement.

Aug 2006 – Feb 2008 · 1 yr 6 mos · Hamirpur, Himachal Pradesh, India · On-site

• Working on various VLSI R&D projects under Special initiative of MHRD Govt of India. Hands on the Latest EDA toolset

Jul 2005 – Sep 2006 · 1 yr 2 mos · Chandigarh Area, India

• Designing of universal protoboard board on which CPLD and FPGA are programmed. Worked on Xilinx high end FPGA (Spartan and Virtex series). Gives technical demonstration of the products (Xilinx high end FPGA and CPLD hardware protoboard).