swapna rani

CEO

Bengaluru, Karnataka, India19 yrs 3 mos experience
Highly Stable

Key Highlights

  • Expert in physical design for next-gen mobile chipsets.
  • Proficient in static timing analysis and sign-off flows.
  • Experienced leader managing engineering teams in complex projects.
Stackforce AI infers this person is a VLSI and ASIC design expert with strong leadership in semiconductor development.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Timing ClosureTeam LeadershipImplementationPower AnalysisPhysical VerificationDebuggingVLSIASICTCLSemiconductorsSoCPower mesh synthesisClock Tree Synthesis and OptimizationDelay and Glitch Cross Talk AnalysisPower Estimation

About

Hands on expertise in physical design Gained good knowledge in STA and Sign off flows Worked on congested and timing convergence designs for next generation mobile chip sets. Experienced in industry standard tools such as Synopsys ICC/ICC2 , Cadence innovus , ATOP, PrimeTime , Tweaker , Calibre and Redhawk.. Good experience in Leading a team of engineers.on all aspects of physical design.

Experience

19 yrs 3 mos
Total Experience
3 yrs 7 mos
Average Tenure
1 yr 1 mo
Current Experience

Next silicon, r&d

PD Head

Apr 2025 – Present · 1 yr 1 mo · India · Hybrid

Static Timing AnalysisPhysical DesignTiming ClosureTeam Leadership

Intel technology india pvt ltd

Engineering Manager

Nov 2016 – May 2025 · 8 yrs 6 mos · Bangalore

Mediatek bangalore

Senior Staff

Jun 2015 – Nov 2016 · 1 yr 5 mos · Bangalore

Broadcom

Technical Lead

May 2014 – Apr 2015 · 11 mos · Bangalore

Open silicon

Lead Engineer

Sep 2012 – May 2014 · 1 yr 8 mos · Bangalore

  • Implemetation , STA, power analysis and physical verification
ImplementationStatic Timing AnalysisPower AnalysisPhysical VerificationPhysical Design

Lsi

Senior Design engineer

Nov 2006 – Aug 2012 · 5 yrs 9 mos · Bangalore

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