Harish Kumar V

Software Engineer

Bengaluru, Karnataka, India9 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Static Timing Analysis and Physical Design.
  • Proficient in multiple EDA tools including Synopsys and PrimeTime.
  • Experience across advanced technology nodes like 7nm and 12nm.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC design and timing analysis.

Contact

LinkedIn

Skills

Core Skills

Static Timing AnalysisPhysical Design

Other Skills

Synopsys PrimetimeSynopsys IC CompilerClock Tree SynthesisCPerlSynopsys Design CompilerFloorplanningTCLVerilogC++

About

*Logic Synthesis on MCMM designs. *Block Level STA (Pre and Post Layout) *Top Level STA (Pre and Post Layout) *Timing Constraints Check *PrimeTime,Design Compiler,Conformal Constraint Designer, TimeVision,Tweaker *7nm,12nm,16nm finfet node *Scripting in Perl and TCL.

Experience

9 yrs 8 mos
Total Experience
3 yrs 3 mos
Average Tenure
5 yrs 3 mos
Current Experience

Qualcomm

3 roles

Staff Engineer

Promoted

Nov 2025 – Present · 5 mos

Static Timing AnalysisSynopsys PrimetimeSynopsys IC CompilerClock Tree SynthesisCPerl+6

Senior Lead Engineer

Nov 2022 – Nov 2025 · 3 yrs

Senior Engineer

Jan 2021 – Nov 2022 · 1 yr 10 mos

Mediatek

2 roles

Senior Engineer

Promoted

Jun 2019 – Jan 2021 · 1 yr 7 mos

Engineer

Jan 2017 – Jun 2019 · 2 yrs 5 mos

Rv-vlsi design center

Physical Design Trainee

Aug 2016 – Jan 2017 · 5 mos · Bengaluru Area, India

  • To understand the ASIC flow and get industry level experience on ASIC design

Education

Global Academy Of Technology

Bachelor’s Degree — Electronics and Communications Engineering

Jan 2012 – Jan 2016

KLE Society's S.Nijalingappa PU college

Pre University — PCMB

Jan 2010 – Jan 2012

Little Lillys English High School

High School

Jan 2000 – Jan 2010

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