Abhishek Guggari

Product Engineer

Bengaluru, Karnataka, India5 yrs 4 mos experience

Highly Stable

Key Highlights

5+ years of experience in physical design engineering.
Expertise in full RTL-to-GDSII implementation.
Specialized in high-performance, low-power designs.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in physical design and verification.

Contact

Skills

Core Skills

Physical DesignStatic Timing AnalysisPpa OptimizationFormal Verification

Other Skills

ICC2FCFormalityconfirmalPTInnovuscerebrusCalibreTCLLECFusion compilerPrime-timeDebuggingLayout Versus Schematic (LVS)Clock Tree Synthesis

About

Physical Design Engineer with 5+ years of experience and 12+ tapeouts across advanced nodes (N6–N2, A14), specializing in high-performance, low-power designs. Supporting PnR flow and methodology innovations at AMD, with expertise in full RTL-to-GDSII implementation and sign-off closure. Focused on PPA optimization and leveraging AI-driven solutions to accelerate convergence and improve design productivity. Experience in formal verification and sign-off checks, including Formality, LEC, and VSI. Tools: FC, ICC2, innovus, PT, Calibre, cerebrus

Experience

5 yrs 4 mos

Total Experience

5 yrs 4 mos

Average Tenure

5 yrs 4 mos

Current Experience

Amd

Silicon design Engineer2

Jan 2021 – Present · 5 yrs 4 mos · Bengaluru, Karnataka, India · On-site

Around 4 years of experience in Asic physical design engineering. Actively working in Methodology team.
Worked in 3nm, 5nm and 6nm technologies. Worked on formal verification and power aware FM (CLP) using confirmal and formality tools. And have a little exposure about DFT.
Also worked on innvous, joules and cerebrus. Have a very good understanding of TCL scripting. Experienced in debugging various design and flow issues
Tools: ICC2, FC, Formality, confirmal, PT, Innovus, cerebrus, quantus, joules, Calibre.

ICC2FCFormalityconfirmalPTInnovus+5