Gauri Shankar Singh — Software Engineer
-DFT Engineer -DFT RTL IP development, DFT SoC Architecture development and integration -Have been part of the DFT team involved in all DFT related activities such as atpg, ictest, coverage improvement, boundary scan, memory bist, automation etc. PE support for silicon bring ups and vector validation. -EEE graduate from NIT Trichy batch 2012.
Stackforce AI infers this person is a Semiconductor and VLSI expert with a focus on DFT methodologies.
Location: Bengaluru, Karnataka, India
Experience: 13 yrs 8 mos
Skills
- Dft
- Analog Circuit Design
- Computer Architecture
Career Highlights
- Expert in DFT RTL IP development and SoC architecture.
- Proficient in ATPG, coverage improvement, and automation.
- Strong foundation in VLSI and Analog Circuit Design.
Work Experience
Qualcomm
Staff Engineer (2 yrs 11 mos)
Intel Corporation
DFT RTL lead (5 yrs 3 mos)
NVIDIA
Senior Engineer (1 yr 7 mos)
Microsemi Corporation
Senior DFT Engineer (5 mos)
PMC-Sierra
Senior DFT Engineer (1 mo)
DFT Engineer (3 yrs 6 mos)
Indian Institute of Technology, Roorkee
robust design of sram chip (2 mos)
Powergrid Corporation of India Ltd
In-plant (0 mo)
Indian Institute of Technology, Guwahati
measuring speed with incoming GPS data (2 mos)
Education
Bachelor of Technology (B.Tech.) at National Institute of Technology, Tiruchirappalli
at 2007 KV OJHAR, NASIK
at 2005 Air Force School Hasimara (West Bengal)
