Amitesh Singh

Software Engineer

Bengaluru, Karnataka, India12 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 3 years of experience in SOC Design Verification.
Expertise in multimedia IP verification for smartphones.
Proven track record in power aware verification.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in SOC and multimedia IP verification.

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Skills

Core Skills

Soc Design VerificationPower Aware VerificationMultimedia Ip VerificationVlsi Design

Other Skills

ACE protocolsAHBAPBASICAXIAssertion Based VerificationCC++ LanguageCadence VirtuosoData StructuresDigital ElectronicsEmbedded SystemsGPUHSPICEHSPICE simulation

About

More than 3 years of experience in SOC Design Verification. SPECIALTIES : • Verification of 2D graphics engine, GPU, JPEG, Security sub-system at SOC level. Low power verification. • Power Aware Verification using Synopsys MVSIM and Cadence IESNLP tools. • Building of Verification Environment using UVM Methodology. • Verification Plan development, Coverage Analysis and Closure. • Power intent verification of SOC using UPF and IESNLP tool . • Knowledge of cache coherency concepts like MESI, MOESI etc. and ACE protocol. TOOLS : • Verdi, Simvision, V-manager, IES, NCSim, IMC, ICCR, Clear case, Perforce LANGUAGES AND METHODOLOGIES : • C, C++, VHDL, Verilog, System Verilog, System Verilog Assertions UVM, Perl. PROTOCOLS : • AHB, AXI, ACE, APB, Q-Channel

Experience

Nvidia

Sr. ASIC Engineer

Nov 2016 – Present · 9 yrs 4 mos · Bengaluru Area, India

Working In CPU verification group.

Verification of 2D graphics engineGPUJPEGSecurity sub-systemLow power verificationSOC Design Verification+1

Samsung research india- bngalore

Sr. Hardware Engineer

Jun 2013 – May 2016 · 2 yrs 11 mos · Bangalore

Joined SRI-B as a Hardware engineer in System LSI group in June 2013 which is responsible for SOC verification of Samsung chipsets for smartphones. worked on 6 SOC verification projects till date and owned complete block level verification responsibilities. Knowledge and working experience of AXI,APB,AHB and ACE protocols. Hands on working experience in Verilog, System Verilog, UVM, SEC-UVM . Expertise in working with multimedia IP's like 2D and 3D graphics engines for smartphone SOC's and security sub-system. Experience working on power aware verification to verify the power intent of the SOC, UPF etc.

SOC verificationAXIAPBAHBACE protocolsVerilog+5

Chang gung university

Internship

May 2012 – Jul 2012 · 2 mos · Taoyuan County, Taiwan

Worked as a research scholar under Prof. I-Chyn Wey of VLSI/CAD lab in Single Event Upset(SEU) or soft error tolerant design which are not affected by high energy gamma and similar particles to be used in space applications and electronic circuitry exposed to radiations. Proposed two improved latch designs (simulated in HSPICE) Iso-DICE and Iso-ST latch.

Single Event Upset (SEU) designHSPICE simulationVLSI Design