Jan 2023 – Jan 2025 · 2 yrs · Bengaluru, Karnataka, India

• Part of the ASG/Ecosystem RnD India BU. Key responsibilities/activities include
• Improving the Synopsys' QiK implementation flows for wider adaptability across CPU ecosystems
• Technology-workflow integration for improved PPA across said ecosystems
• Specialised customer support model for quicker TAT on some lead-partner engagements

Jan 2022 – Jan 2023 · 1 yr · Bengaluru, Karnataka, India

• Part of the Pixel Tensor CPU Silicon team
• Lead PPA push activities for a few sub blocks on the then state-of-the-art Tensor CPU subsystem
• Lead low-power implementation activities for a non-CPU interface IP

Jan 2019 – Jan 2022 · 3 yrs

• Direct contribution towards scaling business for PDG BU
• Help create a scalable implementation team by mentoring, line-managing, and leading various Tier-1, 2 lead-partner engagements
• Technically lead POP projects for several high-profile silicon partners due to drive licensing and royalty revenues for years to come
• Spearheaded the POP/IP roadmap in the Russian and European regions via several successful product deliveries and pre-sales technical marketing
• Responsible for all POP product pre-sales quotes
• Platform Technical lead
• Technical lead for an entire foundation IP platform re-spin on a TIER-2 foundry
• Responsible for successful deliveries of memory compilers, logic architectures, technology kits, etc.
• Product Line Incubation
• Incubating new POP product lines on Cortex M, R class cores & Ethos NPUs
• Responsible for 'engineering' the first-ever commercially available Endpoint-AI POP solution for intelligent IoT devices
• Defining specs for the POPs/PIKs & the IP needed for said low-power applications

Jan 2017 – Jan 2019 · 2 yrs

• Further push into leadership roles for POP product line at PDG BU
• Drove end-to-end lead partner engagements across multiple sites
• Presales, engineering & support for revenue defining engagements
• Defined PPA targets, specs & roadmaps
• Technically lead POP projects to closure with successful execution throughout their lifecycle
• Implementation focus spanning across market segments viz Client mobile, infrastructure, IoT etc.

Jan 2015 – Jan 2017 · 2 yrs

• Implementation of next-generation Arm CPU & subsystem blocks as part of the POP product line
• Exploration of the complete PPA spectrum
• High-performance, Low-power, Area optimised implementations
• Implementations across nodes for key TIER-1 & TIER-2 foundries
• Includes signoff activities - IR/EM, physical verification, In-rush
• Additional responsibilities towards global customer-facing pre-sales technical marketing, post-sales engineering support

Jan 2014 – Jan 2015 · 1 yr · Bengaluru Area, India

• Amongst the first few employees to have joined MTK's Bangalore centre - part of the High performance mobile CPU division.
• Involved with key Tape-outs for some of MTK's flagship Arm- based client CPU blocks.
• Full ownership of key PnR activities on TSMC's flagship nodes at the time - 28nm & 20nm.
• Also gained expertise in some pre-mask functional ECO activities for a re-spin block.

Jan 2012 – Jan 2014 · 2 yrs · Bengaluru Area, India

• Integral part of the OMAP BU.
• Worked extensively on various ASIC flow steps including some signoff activities.
• Gained key insights on Floor planing, Thermal, EM, IR analysis for CPU/GPU partitions.

Dec 2010 – Apr 2012 · 1 yr 4 mos · New Delhi Area, India

• Was actively involved in the day-to-day research and activities with TRF/PhD students in the Laboratory.

Dec 2008 – Feb 2012 · 3 yrs 2 mos · New Delhi Area, India

• Managed the academy for 2 years with successful results; Team of 4 teachers and over 40 junior/high school students.
• Taught senior secondary physics, chemistry and computer Science (C++).