RAKESH BSL

Software Engineer

Bengaluru, Karnataka, India13 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 11 years in semiconductor circuit design.
Expert in circuit characterization and timing analysis.
Proficient in multiple EDA tools and programming languages.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in circuit design and characterization.

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Skills

Core Skills

Circuit DesignCharacterizationTiming CharacterizationSpice SimulationsReceiver Clocking DesignLibrary GenerationI/o Circuit Design

Other Skills

Analog .libs timingNoise characterizationLeakage characterizationRedhawk viewsDecap EstimationDesign and verificationMixed Signal IP'sHSPICESPECTREFINESIMXA simulatorsSTA conceptsTiming reportsAutomation using scriptingAMS verification

About

Design Engineer specialized in Circuit design and Characterization with over 11+ years of experience in Semiconductor Industry Skills : > circuit Design and Verification (IO , Memory and custom digital) > Characterization - NLDM, CCS, Redhawk views > Timing analysis > Basics of layout and Physical Design Languages : > Perl,Shell,C EDA tools: > Finesim ,Spectre ,AMS, Hspice ,XA, BDA Simulators > Cadence Virtuoso schematic and layout editor > SiliconSmart, Primetime > Synopsys Star-RCXT , Xact > Apache totem Projects: > Design and Verification of configurable I/O circuits and reliability verification on I/O blocks > Library characterization of ADC/DAC/PLL/Sensors/Serdes blocks > Design and Verification of Receiver clocking circuits for custom IO blocks

Experience

13 yrs 10 mos

Total Experience

6 yrs 10 mos

Average Tenure

13 yrs 10 mos

Current Experience

Qualcomm

4 roles

Staff Engineer

Promoted

Dec 2023 – Present · 2 yrs 5 mos

Senior Lead Engineer

Dec 2019 – Nov 2023 · 3 yrs 11 mos

> Circuit design and characterization
> Analog .libs timing/Noise/leakage characterization. Worked closely with physical design team to meet the timing @ digital-analog interface of ADC , DAC, PLL, Codec and sensor IPs
> Redhawk - Physical and Electrical (APL) views support for PD for their IP level IR/EM analysis.
> Decap Estimation: Intrinsic, intentional and PG caps from all IPs to avoid power noise in PDN simulations.
> Design and verification of ADC resynchronization block

Circuit designCharacterizationAnalog .libs timingNoise characterizationLeakage characterizationRedhawk views+2

Senior Engineer

Sep 2016 – Nov 2019 · 3 yrs 2 mos

> Expertise in Spice simulations for timing , power and noise characterization of mixed signal IP's
> Worked on timing characterization of Mixed Signal IP's like PLL's, DAC's , ADC's
> Proficient in Using HSPICE, SPECTRE, FINESIM, XA simulators
> Good understanding of STA concepts and well versed in analyzing timing reports
> Improved characterization flow by automating using perl/shell/tcl scripting

Spice simulationsTiming characterizationMixed Signal IP'sHSPICESPECTREFINESIM+4

Serdes characterization Engineer

Jun 2014 – Feb 2016 · 1 yr 8 mos · Bengaluru Area, India

Generating libraries (.libs) , IR and EM analysis using Totem and Redhawk views generation for Analog/Serdes/MIPI blocks

Library generationIR analysisEM analysisTotemRedhawk views generation

Intel corporation

Design Engineer

Feb 2016 – Aug 2016 · 6 mos · Penang, Malaysia

> Design and verification of Receiver clocking
> AMS verification of Receiver clocking
> Worked on design and verification of DLL, differential receiver, Duty cycle adjuster, PI

Receiver clocking designAMS verificationDLL designDifferential receiver designDuty cycle adjuster design