Sumit Gautam — Software Engineer

• Total 10+ yr Experience in Physical Design and SOC floorplan. • Worked on mobile SOC/modem (Heliox) , DDR (HBM) and SERDES IPs. • Handling individual Project with OS. • Experience in 5nm, 7nm, 10nm, 14nm, 28 nm and below technology node • Worked on TSMC ans SAMSUNG foundry. • Winner of All India Mentor Graphics Design Contest, 2014 • Experience in RTL to GDSII implementation and Physical Verification. • Experience in Physical Design Flow on ICC Tool. (Floor Planning, Placement, Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Routing, Congestion and Timing Verification) • Experience in ECO APR flow and Physical Verification (DRC, LVS, ERC, Antenna and LEC) • Experience in Timing library Profiling • Knowledge of all type of Timing and Delay model (NLDM and CCS) • Understanding of Timing and Design constrains (SDC) and Library Profiling.

Stackforce AI infers this person is a VLSI design expert with extensive experience in semiconductor technology.

Location: Bengaluru, Karnataka, India

Experience: 10 yrs 10 mos