Shraddha Padiyar

Software Engineer

Bengaluru, Karnataka, India18 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in power optimization for SoC designs.
Proficient in low-power circuit design and clock distribution.
Experienced in inductance modeling for microprocessor interconnects.

Stackforce AI infers this person is a VLSI design engineer specializing in power optimization and circuit design.

Contact

Skills

Core Skills

Power OptimizationSocCircuit DesignLow-power DesignClock DistributionMicroprocessor Design

Other Skills

Power ModellingPower ConvergencePower reductionCustom Digital Circuit designsHigh speed clock macrosLow power On chip Real Time Clock IPInductance ModellingLow power clock distribution buffersClock grid/Mesh designPhysical DesignTiming ClosureStatic Timing AnalysisCadence VirtuosoVLSICadence Skill

Experience

18 yrs 8 mos

Total Experience

6 yrs 2 mos

Average Tenure

7 yrs 8 mos

Current Experience

Intel corporation

Power and performance Engineer

Sep 2018 – Present · 7 yrs 8 mos

SoC and IP Power Modelling, Power Convergence, Power Optimization, Power reduction

Power ModellingPower ConvergencePower OptimizationPower reductionSoC

Amd

2 roles

Member of Technical Staff

Jan 2016 – Aug 2018 · 2 yrs 7 mos

-Worked on Custom Digital Circuit designs like high speed clock macros, and low power On chip Real Time Clock IP.

Custom Digital Circuit designsHigh speed clock macrosLow power On chip Real Time Clock IPCircuit DesignLow-power Design

Senior Design Engineer

Apr 2011 – Jan 2016 · 4 yrs 9 mos

Clock distribution in 32/28/16 nm Microprocessor design:
Designed the Clock distribution network for distributing clock in 32/28 nm Microprocessor with focus on minimizing power, delay, skew, jitter.
Designed low power clock distribution buffers and the entire clock grid/Mesh.
Inductance Modelling
Inductance modelling on clock interconnects using Fast Henry and W models.Expertise on understanding of return paths and fitting a model mimicking the on-chip behaviour.

Clock distributionInductance ModellingLow power clock distribution buffersClock grid/Mesh designClock DistributionMicroprocessor Design