Ameer Shaik

Software Engineer

Bengaluru, Karnataka, India9 yrs 5 mos experience
Highly Stable

Key Highlights

  • Over 8 years of experience in Physical Design.
  • Expertise in Static Timing Analysis and Physical Verification.
  • Proficient in EDA tools for ASIC design.
Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in Physical Design and EDA tools.

Contact

Skills

Core Skills

Physical DesignCmosStatic Timing Analysis

Other Skills

FloorplanningClock Tree SynthesisTiming closurePhysical VerificationPin placementPower planningPlacementRoutingASICVLSIFPGA prototypingVerilogVerilog-ANC-VerilogLogic Synthesis

About

Worked in Intel as SoC Design Engineer for 2+ years. Worked in Mediatek as a Physical Design Staff Engineer for 4+ years. Worked in Synapse Techno Design as a Physical Design Engineer for 2+ years. - Having Industry oriented knowledge on Physical Design. - 1 year of experience in Bharat Electronics Limited as a GAP Trainee - Good understanding of the CMOS Design, Digital Design, ASIC design flow. - Expertise in Synthesis and Physical Design. - Good knowledge in Static Timing Analysis and Cross Talk Analysis. - Good Understanding of IR-DROP and OCV. - Designed Standard Cells in Full Custom Design at 40nm. Familiar with EDA Tools like : - ICC2/ICC – Floor Planning, Placement,Clock Tree Synthesis(CTS), Route, Star RC - RC Extraction . - PrimeTime/Tempus –Static Timing Analysis and Crosstalk Analysis. - Calibre - Physical Verification (DRC/ERC/LVS/ANT) Techinical Skills: - Languages : Basic Shell Scripting, TCL.

Experience

9 yrs 5 mos
Total Experience
2 yrs 4 mos
Average Tenure
--
Current Experience

Synopsys inc

2 roles

Senior-II

Oct 2023Jul 2024 · 9 mos · On-site

Staff Engineer

Oct 2023Jul 2024 · 9 mos · On-site

Intel corporation

Design Engineer

Sep 2021Sep 2023 · 2 yrs · India

FloorplanningClock Tree SynthesisPhysical DesignCMOS

Mediatek

Staff Engineer

Jun 2017Sep 2021 · 4 yrs 3 mos · Bengaluru, Karnataka, India

Synapse design inc.

Physical Design Engineer

Jan 2015Jun 2017 · 2 yrs 5 mos

  • Block Level Floor Planning, CTS, Timing closure(STA/Tempus), Physical Verification(Calibre/Assura).

Bharat electronics

Graduate Apprentice Trainee

Aug 2010Aug 2011 · 1 yr · Hyderabad, Telangana, India

  • worked as a Graduate Appreciate Trainee

Education

JNTUH

Master of Technology (M.Tech.) — VLSI SYSTEM DESIGN

Jan 2011Jan 2013

Jawaharlal Nehru Technological University

Bachelor's Degree — ELECTRONICS AND COMMUNICATIONS ENGINEERING

Jan 2006Jan 2010

St. Ann's High School

Matriculation — I.C.S.E

Jan 1993Jan 2004

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