Jul 2022 – Oct 2023 · 1 yr 3 mos · Hyderabad, Telangana, India

• Project 3: SAINTL, Samsung Semiconductors India Research Bangalore
• Handled 5nm 3D block, targeted 1GHz, instance count of 1.2M with power switches.
• Built Multipoint H-Tree Clock Spine Structure for all the clocks in all blocks in the chip
• Worked on init and post route DRC analysis and giving effective feedback to the signoff team
• Carried out Initial Netlist Checks, SDC-Sanity Checks and library checks for all the blocks.
• Implemented Magnetic placement and Multi-Point CTS to meet Insertion delays of clocks.
• Developed TCL scripts that check the database, extract design statistics, and errors from logs

Aug 2019 – Aug 2020 · 1 yr · Bangalore

• Project 2: MGRA0, Intel Technologies, Bangalore
• Handled 10nm block, targeted 750MHz, instance count of 850K and 65 macros.
• Placement Timing was being improved using region creation and group path creation.
• The tasks handled were Floorplanning, Place and Route of the design, performing STA and bringing
• the block to timing closure, and cleaning DRC issues at block level.
• Project 1: SPRMCCA0, Intel Technologies, Bangalore
• Full Chip Level timing closure of the block using Context being multiple Instantiated block
• and with Tighter Constraints, Derate Changes compared to previous Tapein
• Closed timing for 17 timing corners for 12 nm methodologies and frequency up to 2.7 GHz
• Have been accountable for manoeuvring primetime quality