sakshi Y.

Data Scientist

Maharashtra, India3 yrs 1 mo experience

AI EnabledAI ML Practitioner

Key Highlights

Expert in VLSI Front-End Design and Verification.
Focused on AI/ML applications in hardware design.
Achieved over 95% functional coverage in projects.

Stackforce AI infers this person is a VLSI and AI/ML specialist in semiconductor design.

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Skills

Core Skills

Vlsi DesignFunctional Verification

Other Skills

VLSI design flowRTL codingVerilogSystemVerilogUVMSynopsys VCSQuestaSimPython (Programming Language)AI/MLPerlSVASTADigital ElectronicsC/C++Printed Circuit Board (PCB) Design

About

I am an engineer with a solid foundation in VLSI Front-End Design & Verification (Verilog, SystemVerilog, UVM, RISC-V) and a developing focus on AI/ML applications in hardware design. My current journey involves strengthening my expertise in Data Science and Machine Learning while exploring their potential to enhance chip design, verification efficiency, and hardware acceleration. With skills spanning digital verification methodologies and emerging AI techniques, I bring a unique perspective to solving complex design challenges. My long-term goal is to contribute to the development of intelligent semiconductor solutions that bridge the gap between hardware and artificial intelligence.

Experience

3 yrs 1 mo

Total Experience

2 yrs 3 mos

Average Tenure

9 mos

Current Experience

Dd-aim

Associate Data Scientist

Aug 2025 – Present · 9 mos

Maven silicon

VLSI Design and verification Engineer

Aug 2024 – Aug 2025 · 1 yr · Bengaluru, Karnataka, India · Remote

Hands-on experience in VLSI design flow, RTL coding in Verilog, and testbench development usingSystemVerilog and UVM.
Built UVM-based verification environments for RTL designs, including UART and AMBA protocols.
Achieved over 95% functional coverage and identified multiple critical bugs during simulations.
Used Synopsys VCS and QuestaSim for testbench development and debugging.
Worked with RISC-V based designs, gaining hands-on experience in their RTL structure and verification strategies.

VLSI design flowRTL codingVerilogSystemVerilogUVMSynopsys VCS+3