Krishna Prabhu — Software Engineer
Career Objective A dedicated and hardworking Physical Design Engineer with an ambition to enhance my skills and knowledge by tackling tough challenges. Core Competency • Good Knowledge on ASIC Flow. (RTL to GDSII) • Total 5.6 year of experience. 4.2 year in Intel and 1.4 year in MediaTek as contractor. • Hands on experience in quickly analyzing the Data-flow model and perform Floor-plan involving High-macro count to meet timing and congestion goals with minimum iterations. • Good Knowledge on Synopsys Design compiler and Fusion Compiler for Synthesis. • Expertise in using Synopsys ICC2 and Fusion Compiler for PNR implementation. • Hands-on experience in Static timing analysis (STA) using Primetime tool (Synopsys STA tool). • Experience in analyzing timing reports with CRPR, MCMM, Clock Skew, Identifying timing exceptions. • Expertise in using Synopsys IC Compiler II (ICC2) tool for Floorplan, Power Plan, Placement, CTS, Routing. • Experience in handling the issues related to Placement with aggressive Timing and Area optimization. • Setup and Hold optimization by using the Synopsys concurrent clock and data optimization algorithm. • Performed CTS and skew optimization to fix setup and hold violations. • Expertise in working multi-voltage design, balancing the clock latency. • Performed Parasitic extraction using STAR-RC tool. • Fixing DRC, LVS, ERC and Antenna to improve the yield. • Experience working LLC (Last Level Cache partition) with clock frequency is around 5GHz. • Expertise in building the U2C (Core to Un-core) and C2U (Un-core to Core) path. • Hands-on experience in Intel Tyche technology and Power Via/backend power structure. • Handling of high pressure and delivery of high-quality results. • Basic knowledge about scripting with TCL and Unix Shell scripting. • Experience in INTEL 10nm, INTEL 14nm, INTEL 7 & INTEL 20A. TSMC 16nm ,28nm 7nm &3nm technology.
Stackforce AI infers this person is a Semiconductor Physical Design Engineer with extensive experience in ASIC design and implementation.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 9 mos
Skills
- Physical Design
- Asic Flow
- Static Timing Analysis
Career Highlights
- Over 5 years of experience in Physical Design Engineering.
- Expertise in multiple advanced semiconductor technologies.
- Proven track record in high-frequency automotive core design.
Work Experience
Tenstorrent
Staff Engineer (RISC-V CPU Back -End Implementation Engineer) (11 mos)
STMicroelectronics
Staff Engineer (Silicon Back -End Implementation Engineer) (1 yr 2 mos)
Technical Lead Engineer (1 yr 3 mos)
Intel Corporation
SoC Design Engineer (4 yrs 5 mos)
MediaTek
Physical Design Engineer (1 yr 3 mos)
Education
Electronics and Communications Engineering at N M A M Institute of Technology, NITTE
Physical Design Engineering at RV College Of Engineering
Diploma in Electronic and communication Engineering at Nitte Education Trust
