Y

Yash Agarwal

Software Engineer

India14 yrs 7 mos experience
Most Likely To SwitchAI Enabled

Key Highlights

  • Led multiple high-impact SoC programs at AMD.
  • Expert in RAS verification and debug automation.
  • Strong mentor and technical anchor in cross-functional teams.
Stackforce AI infers this person is a SoC design and verification expert in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Soc DvTechnical LeadershipSystem Architecture

Other Skills

RAS / MCA Verificationmulti-IP debugSoC-level architecture understandingTest Planning & ExecutionRegression StrategyCoverage ClosureDebug AccelerationAutomation & ScriptingTest PlanningIntelArtificial Intelligence (AI)CodexTeam MentoringTeam MotivationCross-functional Team Leadership

About

SMTS Silicon Design Engineer | RAS Verification Leader | SoC DV | Debug & Coverage Automation | Multi‑program Execution | AI‑assisted Verification | Mentor & Technical Anchor (Bangalore)

Experience

14 yrs 7 mos
Total Experience
5 yrs
Average Tenure
7 yrs 11 mos
Current Experience

Amd

3 roles

Senior Member Of Technical Staff

Promoted

Jul 2021 – Present · 4 yrs 9 mos

  • Over the past several years at AMD, I’ve led and contributed to multiple high‑impact SoC programs across RAS, Core Chiplets, and overall SoC DV. My work spans deep technical ownership, cross‑team leadership,
  • 🔧 Core Skills
  • RAS / MCA Verification, multi‑IP debug, SoC‑level architecture understanding
  • Test Planning & Execution across multiple generations
  • Regression Strategy, Coverage Closure, Debug Acceleration
  • Technical Leadership — mentoring engineers, driving alignment with architects/IP teams
  • Automation & Scripting — regression recovery, post‑processing flows, debug tools, RAS Randomizer
RAS / MCA Verificationmulti-IP debugSoC-level architecture understandingTest Planning & ExecutionRegression StrategyCoverage Closure+4

Member Technical Staff

Promoted

May 2018 – Present · 7 yrs 11 mos

System ArchitectureTest Planning

Design Engineer 1

Sep 2011 – Aug 2016 · 4 yrs 11 mos · Hyderabad Area, India

System ArchitectureTest Planning

Intel corporation

2 roles

Senior PreSi Validation Engineer

Aug 2016 – May 2018 · 1 yr 9 mos

System ArchitectureIntel

Verif

Jan 2016 – Jan 2017 · 1 yr

System ArchitectureTest Planning

Education

National Institute of Technology Warangal

M.Tech — Electronic Instrumentation

Jan 2009 – Jan 2011

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