May 2022 – Apr 2023 · 11 mos · Mountain View, California, United States

• TPU implementation & methodology Lead
• Driving the implementation of Google's FlagShip IP for Pixel SoC.
• Driving the methodology for TPU implementation

Mar 2022 – Jul 2022 · 4 mos · Santa Clara, California, United States

Mar 2020 – Mar 2022 · 2 yrs · Menlo Park, California, United States

• Hands-on Leader driving Physical Design activities towards implementing HardWare Accelerators for various Gaming Devices in sub7nm processes.
• > BackEnd Ownership from Spec Generation (SDC/UPF) , Synthesis , Design Planning, Place & Route, Timing & PV closure.
• > Driving methodology development with multiple CAD tool vendors
• > Driving Hierarchical /Top Level / Chip DesignPlanning/implementation/Integration
• > Leading Provider for tool-agnostic strategies for design convergence
• > Co-Work with Front End & Architecture team to fix design issues
• Hands-on experience on all Major Backend tools

Oct 2019 – Mar 2020 · 5 mos · Ireland

• Managing medium size Physical Design Team for IP delivery for 5G MODEM product lines.
• Individual contributions on Hierarchical Design Ownerships
• Focus on team building & training
• Focus on ECO's for quicker Time to Market
• Focus on Performance & Power of Designs
• Focus on Hierarchical Design Partitioning and Closures

Oct 2018 – Oct 2018 · 0 mo · Singapore

• Invited Guest Lecturer for Computer Architecture Course
• The Lecture was to introduce the origin and trends of computing architectures at a bird's eye view.
• The talk also explained why ASIC and SoC are getting popular; due to the
• advancements in heterogeneous computing architectures and semiconductor technology.
• And it also touch upon hot topics such as Data centres, Artificial Intelligence, Machine Learning and IOT, and what the trends and challenges faced by the computing world to cater to these upcoming product streams.

Feb 2016 – Oct 2019 · 3 yrs 8 mos

• Project and Technology Management with comprehensive project delivery records over last 4years with multiple business units and customers like SONY /MICROSOFT/APPLE

May 2014 – May 2016 · 2 yrs

• Working as Full Chip Owner in Home Entertainment Group
• 1) Responsible for the Full chip Design Planning,Partitioning,Budgeting,CTS,Routing,PV and STA
• 2) Responsible for the R&D on emerging Low Power Methodologies.
• 3) Convergence & Live QA Tools for MultiMillion Chips
• Working as a Full chip owner for 10Million+ chips (28nm/16nm) (Wireless Team)
• 1) Responsible for the Full chip Design Planning,Partitioning Budgeting,CTS,Routing,PV and STA
• 2) Responsible for the R&D on emerging Low Power Methodologies for Wireless Chips.
• 3) Development of Full Chip Low Power Methodology for Low Cost / Fast turn around time.
• Product lines:
• Wifi Routers
• Network Processor
• Working on Physical Design (Netlist to GDS) of ETHERNET SWITCH Products (Data Center Networks Team)
• Handling 3.5Million instance highly congested and timing critical designs.
• Developing advanced CTS algorithms for extreme low latency,skew designs (Also reducing power by 20% )
• Developing tools for Congestion aware Automatic floorplaner for designs more than (1000+ SRAMS)
• Strategies for Faster Closure for High instance count design (>3Million instances)

Jun 2013 – May 2014 · 11 mos · Bengaluru, Karnataka, India

• Worked on 3G & 4G modem and Smart phone SoC's for two generations. Responsible for Netlist to GDS implementation with challenging area and power targets.
• Methodology innovator for unsupervised learning techniques based CAD flows for power reduction, on-demand channel, island based feedthrough etc for aggressive power and area reduction.

Mar 2007 – Apr 2013 · 6 yrs 1 mo · Bengaluru, Karnataka, India

• Worked on implementation from RTL to GDS of various products ranging from Processors, Servers ,Chipsets, X86 Application specific SoC's across the process generations from 90nm to 14nm.
• Worked on methodology development and pioneering for Power reduction and Area Reduction for Better Power Performance of Intel Products.
• Owned & Designed the core for worlds first Solar powered IA-core
• Designed world first cloud computer on a chip
• Developed various Low Power Methodologies for Intel Processors for upto10X Active Power Reduction

Aug 2006 – May 2007 · 9 mos · Bangalore

• Thesis: Research prototype for high throughput bandwidth manager with QoS control using intel network processor and FPGA/ARM subsystem.
• client: MROTEK Bangalore