Naveen NL

Software Engineer

Bengaluru, Karnataka, India7 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in MRAM and SRAM technologies.
  • Proficient in Layout Design and Cadence Virtuoso.
  • Strong background in IC Design engineering.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in memory layout and IC design.

Contact

LinkedIn

Skills

Core Skills

Layout DesignCadence Virtuoso

Other Skills

MRAMSRAMLayout Versus Schematic (LVS)Design Rule Checking (DRC)EMIRFloorplanningSkillTcl

Experience

7 yrs 7 mos
Total Experience
2 yrs
Average Tenure
3 yrs 11 mos
Current Experience

Broadcom inc.

R&D Engineer IC Design 2

Jun 2022 – Present · 3 yrs 11 mos · Bengaluru, Karnataka, India

MRAMSRAMLayout DesignLayout Versus Schematic (LVS)Design Rule Checking (DRC)EMIR+4

Mediatek

Senior Memory Layout Engineer

Nov 2021 – Jun 2022 · 7 mos · Bengaluru, Karnataka, India

Mirafra technologies

Senior Memories Layout Engineer

Oct 2021 – Jun 2022 · 8 mos · Bengaluru, Karnataka, India

Dxcorr design inc

Memory Layout Engineer

Oct 2018 – Nov 2021 · 3 yrs 1 mo

Education

RNS Institute of Technology - India

Bachelor of Engineering - BE

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