Sivaneswaran Sankar — Product Engineer
Currently I started working as a PMIC Analog design engineer at L&T Semiconductor Technologies India. Previously I worked at Samsung SSIR & MediaTek (TW). My area of interest includes Power Management IC design, Energy Harvesting, Analog & Mixed-signal IC design, Low Power VLSI. I completed M.Tech+PhD at IIT Bombay. My thesis titled "Energy Saving Techniques for Energy Constrained CMOS Circuits and Systems" explored various methods of energy saving & energy harvesting for extending the battery life in portable electronic devices. 1. Inductive rectifier for piezo energy harvesting using pre-charge & accumulation (IEEE JSSC, 2022) 2. Switched-capacitor assisted power gating for leakage reduction in digital circuits (IEEE TCAS-1, 2020) 3. NEMS discrete-time amplifier for IQ reduction in Analog Front End (IEEE TED, 2018) 4. Impact on energy reduction in SoC using NEMS power gating (IEEE TED, 2017) Link to my Google scholar page: https://scholar.google.co.in/citations?user=t4NjCnoAAAAJ&hl=en
Stackforce AI infers this person is a specialized engineer in Power Management IC design within the semiconductor industry.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 8 mos
Skills
- Power Management Ic Design
- Analog Ic Design
Career Highlights
- Expert in Power Management IC design and analog circuit development.
- Published multiple research papers in top IEEE journals.
- Strong academic background with M.Tech and Ph.D. from IIT Bombay.
Work Experience
L&T Semiconductor Technologies
Senior Engineer (Analog PMIC) (1 yr 3 mos)
Samsung Semiconductor
Staff Engineer (2 yrs 4 mos)
MediaTek
Senior Design Engineer (1 yr)
National Chiao Tung University
Visiting Researcher (6 mos)
Indian Institute of Technology, Bombay
Mtech+PhD (7 yrs 1 mo)
Education
M.Tech + Ph.D at Indian Institute of Technology, Bombay
Bachelor's degree at Madras Institute of Technology