Sagar Patel — Software Engineer

• 14 years of VLSI industry experience in ASIC Physical Design, Synthesis and other related domains. • Expertise in Synthesis, Place & Route, STA, Physical Verification, Low power implementation and CLP, EM/IR closure. • Hands on experience in taping out blocks of multimillion gate-count SoCs in various deep sub-micron technologies like 28nm, 20nm, 14nm, 10nm, 8nm and 7nm. • Strong scripting experience in TCL for automation of complex tasks. Experienced in writing custom scripts to fix timing, congestion, timing DRV, DRC, dynamic IR, FT implementation flow etc which helped across multiple teams and projects. • Experienced in RTL2Gate and Gate2Gate LEC debug. • Owned CLP review and debug of multiple blocks with complex low power architecture. • Experienced in CECO flow and related debug. • Well versed in PPA convergence of critical designs.

Stackforce AI infers this person is a VLSI and ASIC design expert with a focus on physical design and low-power implementations.

Location: Bengaluru, Karnataka, India

Experience: 14 yrs 5 mos