Jitesh Sanghavi — DevOps Engineer
- ASIC/IC verification professional having 19 years of experience with expertise in diverse verification methodologies, verification process and flows. - Leading ASIC verification projects with multi-site Verification Teams, Architecting and Developing Test Benches and performing Hands-On individual roles. Areas of Expertise Verification planning and execution Architecting and Developing Test Benches Test Case planning and execution SystemVerilog/UVM Methodology based verification e/Specman/eRM Methodology based verification In-Circuit Emulation using Palladium platforms Static verification using SVA/PSL Assertions and Formal tools Protocols : L2 Networking, Ethernet, PCI, PCIe, Bluetooth, WLAN, OCP, AXI, AHB, APB
Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in ASIC methodologies.
Location: Bengaluru, Karnataka, India
Experience: 21 yrs 6 mos
Skills
- Asic Verification
Career Highlights
- 19 years of ASIC verification experience
- Expert in diverse verification methodologies
- Proven leadership in multi-site verification projects
Work Experience
Intel Corporation
ASIC Verification Engineering (3 yrs 10 mos)
MaxLinear
Sr ASIC Verification Manager (2 yrs 9 mos)
Qualcomm
Senior Staff Engineer/Mgr (3 yrs 7 mos)
MediaTek
Staff Engineer (1 yr 8 mos)
Cadence Design Systems
Lead Design Engineer (7 yrs 11 mos)
Insilica Semiconductors
Senior Design Engineer (2 yrs)
Education
Bachelor's degree at Mumbai University Mumbai