Suddarshan S

Director of Engineering

Bengaluru, Karnataka, India19 yrs 10 mos experience
Most Likely To Switch

Key Highlights

  • 19+ years in ASIC verification and digital design.
  • Expert in UVM and eRM methodologies.
  • Proven leadership in building verification teams.
Stackforce AI infers this person is a highly skilled ASIC Verification Engineer with extensive experience in digital design and verification methodologies.

Contact

LinkedIn

Skills

Core Skills

AsicVerification

Other Skills

Ethernet Slim BusUCIe Phy Layer VerificationSystem Memory Controller VerificationUSB Subsystem Verification5G DFE Verification5G Ethernet Switch Verification5G Base Transceiver Station VerificationSystem VerilogUVMEthernet Switch VerificationSoC VerificationCClear Case Project IntegrationeVC DevelopmentASIC Verification

About

19+ years of experience in ASIC verification using SystemVerilog, e/Specman, Verilog, UVM & eRM. • Expertise in creating testbenches using advanced verification methodologies UVM & eRM. • Strong understanding of constrained random stimulus & coverage based auto-checking verification environment. • Efficient in creating schedules, resource plans & executing DV of digital design from concept to tape-out. • Comfortable debugging & verifying Gate level simulation(GLS). • Experience in building & leading a new verification team to verify complex digital blocks for incorporation in mixed signal products. Good Knowledge of UCIe, RISC-V, 5G, PCIe, USB 3.0, ETHERNET SWITCH, MIPI M-PHY, SPI - 4.2, USB 2.0, IEEE 802.3, 10GPON, GPON, and AHB Protocol Standards.

Experience

19 yrs 10 mos
Total Experience
2 yrs
Average Tenure
2 yrs 7 mos
Current Experience

Tech mahindra

Technical Architect

Sep 2023 – Present · 2 yrs 7 mos · Bengaluru, Karnataka, India · Hybrid

  • Ethernet Slim Bus
  • UCIe Phy Layer Verification
  • System Memory Controller Verification
Ethernet Slim BusUCIe Phy Layer VerificationSystem Memory Controller VerificationASICVerification

Intel corporation

SoC Verification Engineer

May 2021 – Sep 2023 · 2 yrs 4 mos · Bayan Lepas, Penang, Malaysia

  • UCIe Phy Layer Verification.
  • USB Subsystem Verification for MTL-M, MTL-S, LNL, PTL.
UCIe Phy Layer VerificationUSB Subsystem VerificationASICVerification

Ericsson

Senior Verification Engineer from Capgemini

Feb 2020 – Mar 2021 · 1 yr 1 mo · Stockholm, Stockholm County, Sweden

Nokia

Sr. Consultant from Capgemini

May 2018 – Jan 2020 · 1 yr 8 mos · Oulu, North Ostrobothnia, Finland

  • Working on 5G Base Tranceiver Station Verification using System Verilog and UVM.
5G Base Transceiver Station VerificationSystem VerilogUVMASICVerification

Capgemini engineering

Senior Design Verification Engineer

Apr 2018 – Apr 2021 · 3 yrs · Bengaluru, Karnataka, India

  • Worked on 5G DFE and 5G Ethernet Switch Verification.
5G DFE Verification5G Ethernet Switch VerificationASICVerification

Mediatek

Staff Engineer

Feb 2014 – Mar 2018 · 4 yrs 1 mo · Fusionopolis, Singapore

  • Ethernet Switch Verification
Ethernet Switch VerificationASICVerification

Qualcomm

Sr.Lead Engineer

Jul 2012 – Jan 2014 · 1 yr 6 mos · Bangalore

  • Responsible for SOC Verification on System Verilog and C.
  • Responsible for Clear Case Project Integration
SoC VerificationSystem VerilogCClear Case Project IntegrationASICVerification

Alcatel-lucent india ltd

Sr.Verification Engineer

Dec 2010 – Jun 2012 · 1 yr 6 mos · Bangalore

Mindtree ltd.

Module Lead

Nov 2008 – Nov 2010 · 2 yrs · Bangalore

  • Responsible for eVC Development.
eVC Development

Capgemini

Design Verification Engineer

Aug 2006 – Oct 2008 · 2 yrs 2 mos · Chennai, Tamil Nadu, India

  • Responsible for ASIC/FPGA Verification and FPGA Validation for USB 2.0
ASIC VerificationFPGA ValidationUSB 2.0ASICVerification

Indian institute of technology, madras

Project Associate

Jan 2006 – Aug 2006 · 7 mos · Chennai Area, India

  • Responsible for developing eVC using specman e.
eVC DevelopmentSpecman eASICVerification

Education

Shanmugha Arts, Science, Technology and Research Academy

M.Tech — VLSI Design

Jan 2003 – Jan 2005

Bharathidasan University

B.E — Computer Science and Engineering

Jan 1999 – Jan 2003

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