Ramu Cherkupally — Director of Engineering
Verilog/VHDL ASIC/ FPGA Design Engineer,Image Processing Expert Software and Hardware Design-RTL development Tools -Synopsys DC, VCS, Prime Time, Cadence NcSim, Xilinx ISE/Vivado, Quartus , ModelSim, Chipscope, Synplify, etc. Verilog - Behavioral & RTL design, solving multiple clock domain design issues, verification, debugging. Specialties: RTL & Behavioral Verilog design, simulation, functional testing and debug,Schematic design,Board Bring up ,Matlab Simulations
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and FPGA technologies.
Location: Hyderabad, Telangana, India
Experience: 15 yrs 10 mos
Skills
- Soc Integration
- Rtl Design
- Low-power Design
- Systemverilog
- Rtl Coding
Career Highlights
- Expert in RTL and Behavioral Verilog design.
- Extensive experience in SOC integration and validation.
- Proficient in low-power design methodologies.
Work Experience
Silicon Labs
Sr.Engineering Manager -IC Design (1 yr 1 mo)
AMD
Senior Member of Technical Staff (2 yrs 8 mos)
Intel Corporation
System-on-Chip Design Engineer (3 yrs 7 mos)
Synaptics Incorporated
Senior Application Specific Integrated Circuit Design Engineer (1 yr 7 mos)
Moschip Semiconductor Technology Ltd.
Sr Engineer-ASIC (1 yr 2 mos)
Analinear Techonology
Lead Design Engineer (2 yrs 8 mos)
Design Engineer (3 yrs 1 mo)
Education
M.E at Birla Institute of Technology, Mesra
B.Tech at Jawaharlal Nehru Technological University
