May 2022 – Jun 2022 · 1 mo · Hyderabad, Telangana, India

May 2019 – Apr 2022 · 2 yrs 11 mos · Noida, Uttar Pradesh, India

• I have worked on AMBA based AXI protocol. Got hands-on experience on FPGA Prototyping on Xilinx zedboard. Work on IP level verification i.e Creating UVM based verification env, coded test sequences and also functional coverage model.
• Creation of Uvm model for simple RW to quirky register behaviors like lock,aliases,shadows,Ro-wo pair.
• project - IEEE Ethernet 40/100G
• Mac : media access control Rs: Reconciliation sublayer PCS: Phycial control sublayer PMA: Physical management attachement PMD : physical management dependent
• coded for PCS monitor
• coded for testcases and sequence for PCS
• debug and some fixes

May 2018 – May 2019 · 1 yr · Noida, Uttar Pradesh, India

• work as a Design/Verification Engineer on IP/SOC level and get involved in challenging projects which have immense learning and growth opportunities.

Mar 2017 – Apr 2018 · 1 yr 1 mo · Greater Delhi Area

• FIFO: designing in verilog
• FIFO: verification using system verilog
• FIFO: Implemented Verification Enviroment Using UVM
• AMBA-3 APB (Advanced Peripheral Bus) v2.0 Using Verilog
• FPGA Implementation Of Digital Alarm Clock Using Verilog
• UART (Universal Asynchronous Receiver/Transmitter)
• i2c protocol,
• spi protocol

Aug 2015 – Jan 2017 · 1 yr 5 mos · Ludhiana, Punjab, India

May 2013 – Dec 2013 · 7 mos · Noida, Uttar Pradesh, India