Jul 2016 – Dec 2016 · 5 mos · Bangalore

• Objective of the project is porting of system Verilog assertions according to PCIE controller and writing equalization checkers for gen3/4 for both coefficients tuning method: FOM and DIR. For porting of System Verilog Assertions, Perl script has been written for text manipulation to convert System Verilog Assertions according to respective PCIE controller. Script can be used in future for similar work. Corner Test cases for equalization has been written. Equalization checkers have been written for gen3 and extended to gen4. Checks are written for LTSSM entry-exit condition, Coefficients check, DIR flow check, Phase 2 iterations and etc.