Sep 2012 – Sep 2014 · 2 yrs · Bengaluru Area, India

• Technical direction for PD team which is handling multiple IPs (DDR, PCIe, SerDes, USB, PLL etc.,), test chips at 28nm, 20nm and below tech nodes.
• Team building, Ramp-up, supporting multiple vertical teams across AMD.

Feb 2012 – Sep 2012 · 7 mos · Bengaluru Area, India

• Handling all the physical design implementation aspects of complex IPs at 28nm and below. Working with diversified SoC teams to resolve all the interface related issues.

Jan 2010 – Feb 2012 · 2 yrs 1 mo · Bangalore, India

• Technical Management of all Physical Design activities at STE for complex SoCs at 40nm tech node and below.
• Top level technical direction, day-to-day execution, team building and successful tape-outs.

Dec 2008 – Feb 2010 · 1 yr 2 mos

• Physical Design implementation of complex SoC / ASICs at 65nm and below tech nodes.

Jan 2007 – Jan 2008 · 1 yr

• Part of WLAN physical design team and involved in 2 chips at 65nm.

Jul 2006 – Dec 2008 · 2 yrs 5 mos

• Technical management of PD team consisting of ~20 engineers.
• Block and Top level execution of Netlist-GDSii flow at 90nm and below tech nodes.
• Selection of right talent , retaining and mentoring them.

Jun 2004 – Jun 2006 · 2 yrs

• Identified as local low power expert at Bangalore from Cadence side.
• Part of Expert User Group resolving the critical issues of strategic customers likes IBM, Freescale etc.,
• Later moved to AMS Kit and responsible for the successful integration of digital part of a mixed signal chip.

Jan 2003 – Jan 2004 · 1 yr

• One of the core PD members of Open-Silicon.
• Responsible for the first two successful tape-outs.

Jan 2001 – Jan 2003 · 2 yrs

• Deputed at TI India and part of Pyramid team resolving the flow issues.
• Managing the team of 6 engineers at the client place.
• Got appreciation at TI for the successful release of Pyramid Cycles.

Jan 2001 – Jan 2003 · 2 yrs

• Worked with TI ASIC team for the Pyramid flow stabilization.
• Worked on MAGMA flow extensively.