Nithyanandham Kotti — Software Engineer
I have around 18 years of VLSI Test domain experience during which I have worked as part of complex SoC designs in AI, server, Wireless, Networking and Automotive Business units. I have gained expertise in entire gamut of DFT right from DFT Architecture definition, DFT implementation and DFT verification for SoCs and complex sub-systems. • Expertise in dealing with end to end DFT activities for complex multi-million gate SoCs • DFT Architecture/Planning: SCAN Architecture Planning, Test Modes Clocking, Memory Test Strategy, JTAG • Scan Insertion, DFT insertion at RTL/netlist level, Memory BIST insertion • ATPG, MBIST Pattern Generation & verification through unit-delay and timing simulations • Proficiency in DRC analysis and Test Coverage improvement • Spyglass DFT checks • Logic Equivalence checks for pre versus post DFT insertion • DFT mode STA constraint development & support Timing Closure/Back End Teams • Experience in bringing up DFT patterns on silicon floor
Stackforce AI infers this person is a VLSI expert with extensive experience in DFT for complex SoC designs.
Location: Bengaluru, Karnataka, India
Experience: 19 yrs 7 mos
Skills
- Dft
- System On A Chip (soc)
Career Highlights
- 18 years of expertise in VLSI Test domain.
- Led DFT integration for complex multi-million gate SoCs.
- Proficient in DFT architecture and verification.
Work Experience
Marvell Technology
Principal Engineer - DFT (9 mos)
AMD
Senior Member Of Technical Staff - DFT (3 yrs 7 mos)
Intel Corporation
DFT Lead (3 yrs 9 mos)
Microchip Technology
Principal Engineer - DFT (3 yrs 9 mos)
Mirafra Technologies
Member of Technical Staff - DFT (2 yrs 4 mos)
Infosys
Technology Analyst - DFT (10 mos)
Wipro Technologies
Senior Project Engineer (4 yrs 7 mos)
Education
M.S. at Birla Institute of Technology and Science, Pilani
B.E. at Sri Venkateswara College of Engineering and Technology