Nithyanandham Kotti

Software Engineer

Bengaluru, Karnataka, India19 yrs 7 mos experience
Highly Stable

Key Highlights

  • 18 years of expertise in VLSI Test domain.
  • Led DFT integration for complex multi-million gate SoCs.
  • Proficient in DFT architecture and verification.
Stackforce AI infers this person is a VLSI expert with extensive experience in DFT for complex SoC designs.

Contact

Skills

Core Skills

DftSystem On A Chip (soc)

Other Skills

SoC Scan MicroarchitectureScan IP coding and verificationSubsystem DFT MicroarchitectureDFT integration of PCIe 5 PHYSpyglass DFT checksScan InsertionATPGDFT Architecture planningCompressionMemory BIST InsertionLogic Equivalency ChecksDFT mode STA constraintsMBIST/SCAN verificationSilicon Bring upATE support

About

I have around 18 years of VLSI Test domain experience during which I have worked as part of complex SoC designs in AI, server, Wireless, Networking and Automotive Business units. I have gained expertise in entire gamut of DFT right from DFT Architecture definition, DFT implementation and DFT verification for SoCs and complex sub-systems. • Expertise in dealing with end to end DFT activities for complex multi-million gate SoCs • DFT Architecture/Planning: SCAN Architecture Planning, Test Modes Clocking, Memory Test Strategy, JTAG • Scan Insertion, DFT insertion at RTL/netlist level, Memory BIST insertion • ATPG, MBIST Pattern Generation & verification through unit-delay and timing simulations • Proficiency in DRC analysis and Test Coverage improvement • Spyglass DFT checks • Logic Equivalence checks for pre versus post DFT insertion • DFT mode STA constraint development & support Timing Closure/Back End Teams • Experience in bringing up DFT patterns on silicon floor

Experience

19 yrs 7 mos
Total Experience
3 yrs 1 mo
Average Tenure
9 mos
Current Experience

Marvell technology

Principal Engineer - DFT

Aug 2025Present · 9 mos

Amd

Senior Member Of Technical Staff - DFT

Jan 2022Aug 2025 · 3 yrs 7 mos

Intel corporation

DFT Lead

Apr 2018Jan 2022 · 3 yrs 9 mos

  • SoC Scan Microarchitecture
  • Scan IP coding and verification
  • Subsystem DFT Microarchitecture
  • DFT integration of PCIe 5 PHY
  • Spyglass DFT checks
  • Scan Insertion and ATPG
SoC Scan MicroarchitectureScan IP coding and verificationSubsystem DFT MicroarchitectureDFT integration of PCIe 5 PHYSpyglass DFT checksScan Insertion+3

Microchip technology

Principal Engineer - DFT

Jul 2014Apr 2018 · 3 yrs 9 mos

  • DFT Architecture planning
  • Compression, Scan Insertion, ATPG
  • Memory BIST Insertion, Logic Equivalency Checks, DFT mode STA constraints
  • MBIST/SCAN verification
  • Silicon Bring up and ATE support
DFT Architecture planningCompressionScan InsertionATPGMemory BIST InsertionLogic Equivalency Checks+6

Mirafra technologies

Member of Technical Staff - DFT

Mar 2012Jul 2014 · 2 yrs 4 mos

  • Scan Insertion and ATPG
  • ATPG coverage improvement for low coverage subchips
  • Scan Verification
  • Pattern Optimization
  • ATE Support
Scan InsertionATPGATPG coverage improvementScan VerificationPattern OptimizationATE Support+1

Infosys

Technology Analyst - DFT

Apr 2011Feb 2012 · 10 mos

  • LBIST pattern generation and verification
  • JTAG 1149.1/6 pattern generation and verification
  • SERDES BIST verification
LBIST pattern generationJTAG pattern generationSERDES BIST verificationDFT

Wipro technologies

Senior Project Engineer

Sep 2006Apr 2011 · 4 yrs 7 mos

  • DFT and Test
DFTTest

Education

Birla Institute of Technology and Science, Pilani

M.S. — Microelectronics

Jan 2008Jan 2009

Sri Venkateswara College of Engineering and Technology

B.E. — Electronics and Communication

Jan 2002Jan 2006

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