Hari Krishna Balupala

Software Engineer

Kurnool, Andhra Pradesh, India8 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Emerging star award in March 2022
Boost and Spark awards for excellence in 2021 and 2020
Delivered Versal and Ultrascale+ chips for 2 consecutive years

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in FPGA and VLSI technologies.

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Skills

Core Skills

Low Power DesignFpga Design Verification

Other Skills

VerilogConformal LECIntegrated Circuits (IC)System on a Chip (SoC)Application-Specific Integrated Circuits (ASIC)Field-Programmable Gate Arrays (FPGA)VLSICHTMLMatlabSystemVerilogStatic Timing AnalysisDFTVery-Large-Scale Integration (VLSI)

About

VLSI Design Engineer with 7 years of experience in 7nm, 16nm and 65nm FPGA Chip/Block Design Verification and error control coding. Skills • Low Power Design (writing UPF’s for Power management using Power switches, Level Shifter, Isolation and Retention strategies). • Low Power Verification (Static verification using CLP and Dynamic Verification using VCS). • Delivered Xilinx Homogeneous and Heterogeneous designs in system-level integration. • Ultra RAM RTL Design, Verification (Smoke test, Compilation, Lint). • Pattern Generation and Validation of Memory on Silicon. • Formal Verification (LEC - RTL vs RTL, RTL vs Netlist, Netlist vs Netlist at Chip/Block level). • Behavioural RTL Verification (RTL vs Spice Netlist). • FPGA ARM ROM’s functional Verification using ESP. • BSDL generation • Error control codes designs like Hamming codes, BCH codes. Career highlights • Emerging star award in March 2022. • Boost award and Spark award for excellence in 2021, 2020. • Delivered Versal, Ultrascale+ family series chips for 2 consecutive years in 2020-22.

Experience

8 yrs 4 mos

Total Experience

4 yrs 2 mos

Average Tenure

4 yrs 2 mos

Current Experience

Amd

Senior Silicon Design Engineer

Feb 2022 – Present · 4 yrs 2 mos · Hyderabad

Deliver RTL checks and ROM’s for all FPGA tapeouts.
Low power design and Verification: Ultra RAM Blocks for next generation FPGA products.
Conformal ECO on various integration Modules

VerilogConformal LECLow Power DesignFPGA Design Verification

Xilinx

3 roles

Design Engineer II

Promoted

Jun 2020 – Feb 2022 · 1 yr 8 mos

Significant contribution to Premium and Prime series Tapeouts to verify LEC, CLP, ESP, ROM’s at Chip/Block level.
Reported various issues with Cadence and Synopsys in various flow’s.
Low Power Design & Verification: FPGA Chip/Block level for Next Generation FPGA's.
Achieved ‘Emerging Star’ award for contribution to 7nm, 16nm and 65nm Tapeouts.
Best Presentation Award for Galois Field Arithmetic Operations using Xilinx FPGAs in Cryptography issued by 2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS).

VerilogConformal LECLow Power DesignFPGA Design Verification

Design Engineer

May 2018 – Jun 2020 · 2 yrs 1 mo

RTL logic implementation of FPGA Memory Blocks (URAM, BRAM).
Generated partial reconfiguration and char functional patterns for FPGA’s Validation.
Validation & Characterization of memory blocks features like Error detection and correction, Partial configuration, Content Initialisation and Readback on various FPGA boards at different voltages.
Formal Verification of various FPGA Chip/Blocks (RTL vs Schematic) in 7nm, 16nm & 65nm.
Low Power Design and Verification (Writing UPF's at Chip/Block level) for all tapeouts.
Generated die BSDL and Package BSDL files for all taepouts and verified with JTAG tech.
Implemented various Galois field arithmetic operations like inverse, division for AES S-Box.
Achieved ‘Spark award for Excellence’ for finding bugs in Formal Verification flows.

VerilogConformal LECLow Power DesignFPGA Design Verification

Intern

Dec 2017 – May 2018 · 5 mos

Basic understanding of 7nm & 16nm FPGA architecture and various flow’s.
RTL design and Verification of Multiple bit detect and Multiple bit correct BCH Code, Double bit detect and correct Hamming Code in Questasim.

VerilogConformal LEC

Mentor graphics

Trainee

Jun 2017 – Jul 2017 · 1 mo · Bengaluru Area, India

Trainee in Verification of Electronic Design and Systems using SystemVerilog and concepts of UVM.
Training included Concepts of System Verilog, Constraint Random Verification, OOPs, Coverage (code and functional coverage) and hands-on writing designs and System Verilog Test bench environments.

VerilogIntegrated Circuits (IC)

Isro - indian space research organisation

Summer Intern

May 2017 – Jun 2017 · 1 mo · Chandigarh Area, India

Worked as a project trainee at Semiconductor Laboratory Chandigarh.
VSLI industry exposure to various tools used by Mentor Graphics in SCL - Mentor forum.

Integrated Circuits (IC)System on a Chip (SoC)