Atmiya Chauhan — Software Engineer
Inefficiency stands as the largest employer globally. Removing it too swiftly with technology can lead to significant civil unrest.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Timing Analysis.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 10 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expert in Physical Design and Static Timing Analysis.
- Proven experience in reliability verification processes.
- Strong background in VLSI Design from top institutions.
Work Experience
Synopsys Inc
Applications Engineering, Sr 1 (4 yrs 2 mos)
Intel Corporation
SoC Design Engineer (3 yrs 8 mos)
Graduate Technical Intern (1 yr)
Education
Master of Technology - MTech at Nirma University
Bachelor's degree at A. D. Patel Institute Of Technology, Karamsad 001
Diploma at Government Polytechnic Ahmedabad
Primary at Jay Ambe Vidyalay, Vadodara
