Febin Sebastian

Software Engineer

Bengaluru, Karnataka, India7 yrs 5 mos experience
Highly Stable

Key Highlights

  • Expert in DFT and SoC design methodologies.
  • Proficient in BIST and ATPG techniques.
  • Strong background in VLSI and digital electronics.
Stackforce AI infers this person is a DFT and VLSI specialist in the semiconductor industry.

Contact

febin89@gmail.comLinkedIn

Skills

Core Skills

DftSystem On A Chip (soc)

Other Skills

Automatic Test Pattern Generation (ATPG)Universal Verification Methodology (UVM)Application-Specific Integrated Circuits (ASIC)Digital ElectronicsVery-Large-Scale Integration (VLSI)VerilogCSVRTL DesignBISTMbist

Experience

7 yrs 5 mos
Total Experience
2 yrs 6 mos
Average Tenure
2 yrs 4 mos
Current Experience

Intel corporation

DFT Design Engineer

Dec 2023 – Present · 2 yrs 4 mos · Bengaluru, Karnataka, India · On-site

Automatic Test Pattern Generation (ATPG)DFTSystem on a Chip (SoC)Universal Verification Methodology (UVM)Application-Specific Integrated Circuits (ASIC)Digital Electronics+5

Qualcomm

Senior DFT Engineer

Aug 2022 – Nov 2023 · 1 yr 3 mos · Chennai, Tamil Nadu, India · On-site

BISTDFT

Perfectvips

DFT Engineer

Sep 2018 – Jul 2022 · 3 yrs 10 mos · Bengaluru Area, India

BISTDFT

Education

Karunya Institute of Technology and Sciences

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2013 – Jan 2017

Maven Silicon

VLSI

Jan 2018 – Jan 2018

Stackforce found 100+ more professionals with Dft & System On A Chip (soc)

Explore similar profiles based on matching skills and experience

Shikha Shrivastava

Shikha Shrivastava

SoC Design Engineer

at Intel Corporation

Hyderabad, India6 yrs 9 mos exp
Automatic Test Pattern Generation (ATPG)Scan Insertion
Prem Kumar T

Prem Kumar T

Staff Engineer

at Qualcomm

Cork, Ireland10 yrs 6 mos exp
Vikas Sethi

Vikas Sethi

Senior Director, SoC Design & Design Tech.

at MIPS

Bengaluru, India29 yrs 8 mos exp
Nivethitha A

Nivethitha A

Senior Engineer

at Synopsys Inc

Bengaluru, India5 yrs exp
VerilogFloorplanningField-Programmable Gate Arrays (FPGA)
BK

BalaKrishna K

SoC DFT LEAD

at Google

Bengaluru, India19 yrs 9 mos exp
Vinod Kumar G

Vinod Kumar G

Technical Lead

at Astera Labs

Bengaluru, India8 yrs 8 mos exp
AM

Ajesh M P

Automation Engineer

at TESSMOTECH PRIVATE LIMITED

Ernakulam, India9 yrs 10 mos exp
Hari Krishna Balupala

Hari Krishna Balupala

Senior Silicon Design Engineer

at AMD

Kurnool, India8 yrs 4 mos exp
Low Power DesignFPGA Design Verification