Naresh Dandeti

CEO

Bengaluru, Karnataka, India11 yrs 4 mos experience

Highly Stable

Key Highlights

7.5 years of experience in VLSI design.
Expert in full-chip and block-level implementation flows.
Proven track record in achieving targeted PPA.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in physical design methodologies.

Contact

Skills

Core Skills

P&rClockingDesign Optimization

Other Skills

RC ExtractionDesign Rule Checking (DRC)CVLSIPerlStatic Timing AnalysisTCLSoCIR Drop Analysis

About

I'm Master's in MSc Electronics & Instrumentation at Sri Krishnadeveraya University College (campus), having experience of 7.5 years. I am currently working as a Lead Engineer and taking care of PPA achivement for core hardening. I have worked on full-chip and block level implementation flows including synthesis, floor-planning, PnR to sign-off flows for STA, IR and low power verification. Area Of Interest : Full-Chip floor-planing , Sign-off timing (STA), Low power development and implementation. Develop physical design methodologies for full chip and block execution to improve sign-off closure.

Experience

11 yrs 4 mos

Total Experience

2 yrs 9 mos

Average Tenure

Current Experience

Intel corporation

Lead

Jan 2018 – Jan 2024 · 6 yrs · Bengaluru

ClockingP&R

Qualcomm

Engineer Senior

Apr 2016 – Jan 2018 · 1 yr 9 mos · Bengaluru

Sr Lead Engineer

P&RDesign Optimization

Arm

Consultant Sr Design Engineer

Sep 2015 – Mar 2016 · 6 mos · Bengaluru

I worked in a Benchmarking (core hardening) team at ARM.
The Benchmarking team will work from RTL to Signoff to achieve Targeted PPA at different technologies .

P&RDesign Optimization