Madhusudan Sarda

Director of Engineering

Bengaluru, Karnataka, India18 yrs 11 mos experience
Highly Stable

Key Highlights

  • Led 15+ successful chip tapeouts at NVIDIA
  • Managed a team of over 70 engineers
  • Expert in SOC design and methodology
Stackforce AI infers this person is a Hardware Engineering expert in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Soc DesignMethodologySoc IntegrationPerformance MonitoringClocks DesignVerificationResets DesignAsic Design

Other Skills

ClocksResetsPadringDebug FabricIP integrationClockingDebug IPsAssemblyClocking implementationSafety featuresSafety work-productsDigital blocksHybrid PLLsClock DistributionRouting

About

Working in the capacity of Director of Hardware Engineering at Nvidia Graphics, having responsibility of SOC global functions - Clocking, Resets, Padring, Performance Monitoring, Debug IPs as well as SOC integration and Assembly. Having 11+ Years of experience in building teams from scratch and managing teams focused on Design, Verification, Methodology, Timing Sign-off. Currently managing a 70+ person strong team. Highly technical and having strong grasp on both front-end and back-end concepts - hands-on experience on RTL-Design, Physical-Design, STA, Safety features and work-products. Have worked on 15+ successful tapeouts of chips focused on Nvidia's MCP, Tegra, CPU and GPU-Switch products while being in lead (Clocks/Resets)/Managerial capacity for 10+ chips.

Experience

18 yrs 11 mos
Total Experience
18 yrs 11 mos
Average Tenure
18 yrs 11 mos
Current Experience

Nvidia

6 roles

Director of Hardware Engineering

Promoted

Jun 2023 – Present · 2 yrs 10 mos

  • Driving SOC Design and Methodology for building Tegra processors with focus on development of distributed functions such as Clocks, Resets, Padring, Performance Monitoring, Debug Fabric as well as IP integration.
SOC DesignMethodologyClocksResetsPadringPerformance Monitoring+2

Senior Manager

Promoted

Oct 2018 – May 2023 · 4 yrs 7 mos

  • Having responsibility of SOC global functions -
  • Clocking, Resets, Padring, Performance Monitoring, Debug IPs as well as SOC integration and Assembly for Tegra SOCs.
ClockingResetsPadringPerformance MonitoringDebug IPsSOC integration+1

Manager

Dec 2014 – Sep 2018 · 3 yrs 9 mos

  • Built strong Clocks Design/Verification team from scratch at Bangalore Design Center (BDC).
  • Executed Clocking implementation for multiple projects from BDC.
  • Drove various Clocking related Safety features needed for Automotive market and created safety work-products for assessment.
Clocks DesignVerificationClocking implementationSafety featuresSafety work-products

Senior Design Engineer

Promoted

Oct 2010 – Dec 2014 · 4 yrs 2 mos

  • Worked on Clocks and Resets Design for multiple generation of Tegra chips.
  • Designed Digital blocks for Hybrid PLLs, Owned Clock Distribution/Routing for SOC Clocks and drove various IP Clocking implementation and SOC Clocking features.
  • Worked as a lead for Clocks/Resets Design from POR process to Bring-up.
ClocksResets DesignDigital blocksHybrid PLLsClock DistributionRouting+2

ASIC Design Engineer

Jul 2007 – Sep 2010 · 3 yrs 2 mos

  • Started off career with NVIDIA in ASIC Design group. In this duration, I worked on:
  • Bring-up activities related to CPU/Memory interface for C73/MCP79.
  • Developing System Verilog based verification environment for PCIE-Gen3.
  • Owned the clocks implementation and distribution for MCP/Tegra chips.
ASIC DesignCPU/Memory interfaceSystem VerilogPCIE-Gen3Clocks implementationDistribution+1

Internship

Jan 2007 – Jun 2007 · 5 mos

  • Worked here in the final semester of graduation as part of Practice School program.
  • Owned Memory qualification on Silicon from ASIC side for C55.
Memory qualificationASIC

Bhabha atomic research centre

Summer Intern

Jun 2005 – Jul 2005 · 1 mo

Education

Birla Institute of Technology and Science, Pilani

BE (Hons) — Electronics

Jan 2003 – Jan 2007

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