Juhi .

Product Engineer

Bengaluru, Karnataka, India8 yrs experience
Highly Stable

Key Highlights

  • Expert in UVM and SystemVerilog methodologies.
  • Strong foundation in VHDL and Verilog languages.
  • Proven problem-solving and debugging capabilities.
Stackforce AI infers this person is a Design Verification Engineer with expertise in VLSI and digital electronics.

Contact

Skills

Other Skills

VHDLVerilogsystem verilogFPGAAssertion Based VerificationUVMCMOSDigital ElectronicsN+ CertifiedStatic Timing AnalysisJavaOperating SystemsPerlC++VLSI

About

Hands on experience in UVM methodology based test bench development and Verification. Hands on experience in SystemVerilog HVL based test bench development and Verification. Strong knowledge in Verilog HDL and VHDL language. Hands on experience in OSVVM methodology based test bench development and Verification. Good Debugging skills. Good logical and innovative thinker. Good problem solving skills. Good interpersonal skills. A good team player.

Experience

8 yrs
Total Experience
2 yrs
Average Tenure
--
Current Experience

Amd

Senior Design Engineer

May 2019Mar 2022 · 2 yrs 10 mos · India

Mirafra technologies

Verification Engineer

Sep 2015May 2019 · 3 yrs 8 mos · Greater Bengaluru Area

Vecima networks inc.

FPGA Developer

Oct 2014Aug 2015 · 10 mos · Mangaluru, Karnataka, India

Atria logic inc.

Member Technical Staff 1

Sep 2013Jun 2014 · 9 mos · Chennai

Education

MIMIT/PTU

B.TECH — ECE

Jan 2009Jan 2013

MAVEN SILICON

DESIGN AND VERIFICATION — VLSI

Jan 2013Jan 2013

KENDRIYA VIDYALYA

Jan 1997Jan 2009

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