Juhi . — Product Engineer
Hands on experience in UVM methodology based test bench development and Verification. Hands on experience in SystemVerilog HVL based test bench development and Verification. Strong knowledge in Verilog HDL and VHDL language. Hands on experience in OSVVM methodology based test bench development and Verification. Good Debugging skills. Good logical and innovative thinker. Good problem solving skills. Good interpersonal skills. A good team player.
Stackforce AI infers this person is a Design Verification Engineer with expertise in VLSI and digital electronics.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs
Career Highlights
- Expert in UVM and SystemVerilog methodologies.
- Strong foundation in VHDL and Verilog languages.
- Proven problem-solving and debugging capabilities.
Work Experience
AMD
Senior Design Engineer (2 yrs 10 mos)
Mirafra Technologies
Verification Engineer (3 yrs 8 mos)
Vecima Networks Inc.
FPGA Developer (10 mos)
Atria Logic Inc.
Member Technical Staff 1 (9 mos)
Education
B.TECH at MIMIT/PTU
DESIGN AND VERIFICATION at MAVEN SILICON
at KENDRIYA VIDYALYA