May 2023 – Nov 2023 · 6 mos · Hyderabad, Telangana, India · On-site

• Driving Innovations in Physical Design to Enhance Power Efficiency of Imagination GPUs

Mar 2022 – May 2023 · 1 yr 2 mos · Markham, Ontario, Canada

• Played a key role in the Full-Chip Timing Closure of a Large (>200mm²), High-Speed (>2GHz) SoC for desktop applications. Additionally, gained valuable insights into the implementation and signoff challenges associated with 3D ICs, further enriching expertise in advanced semiconductor technologies.

Jun 2018 – Dec 2021 · 3 yrs 6 mos

• I successfully built and nurtured a high-performing physical design team, which consistently delivered on the company's most critical projects. I mentored team members, guiding them in areas such as Project Management, Top Place and Route, Block Coordination, and Block Place and Route, based on their individual experiences, skills, and aspirations.
• Additionally, I managed high-stakes, high-visibility projects with a hands-on approach, overseeing all aspects of planning, execution, and reporting to top management. My leadership ensured the successful completion of these projects, demonstrating both strategic vision and practical expertise in project management

Jul 2017 – May 2018 · 10 mos

Jul 2014 – Jun 2017 · 2 yrs 11 mos

• I was entrusted with the first implementation of MediaTek's LTE-Advanced Modems for three successive generations (Gen91, 92, 93). Despite the uncertainties posed by new designs and cutting-edge process nodes such as N20, N16, N12, and N7, I successfully completed five modem projects on time

Jan 2013 – Jun 2014 · 1 yr 5 mos

• Played a crucial role in the Modem IP team as the Block Coordinator, resolving critical technical challenges and ensuring the smooth progression of the project. Demonstrated expertise and leadership in addressing complex issues, contributing significantly to the team's success

Apr 2012 – Dec 2012 · 8 mos · Giheung, South Korea

• Responsible for hierarchical full chip level physical design and signoff of SSD Memory Controllers involving complex design methodologies viz. Power Gating, Multi-Row IOs and FlipChip
• [Selected Projects]
• o Top level flat physical design and signoff of DRAM-less SATA SSD controller (size 12.25 mm2, Process 32nm, instance count 1.5 million, Power Gating, 5 power domains) in EDI.
• o Developed GUI utility in Tk for fast, accurate and comprehensive fixing of max transition violations interactively in EDI.

Mar 2008 – Mar 2012 · 4 yrs · Giheung, South Korea

• Responsible for Physical Implementation (Cadence and Magma based) and Sign-off of multi-million instance ASICs from diverse domains (DTV, Printers, and Micro-controllers).
• [Selected Projects]
• o Top level hierarchical physical design of PCIe based SSD controller (size 28.1mm2, Process 32nm, instance count 4.9 million, 8 subblock, PMOS Power Gating, 5 power domains, Flipchip) in EDI. The design had complex CTS structure and power gating scenarios. Developed custom scripts for low power implementation and checking. Used triple row IOs to reduce size of pad-limited design.
• o Top level flat physical design and signoff of 3D processor for car navigation (size 17.2 mm2, Process 65nm, instance count 1.13 million) in EDI. Fixed timing by developing flow to find the optimal common clock tree driving cell among a list of clock pins to apply useful skew.
• o Top level flat physical design of channel decoder for DBS, E1 & E2 (size 56.2/68.9 mm2, Process 65 nm, instance count 2 million, memory count 437/401) in Talu. Cleared ECO stage congestion by developing flow to replace string of hold buffers with delay cells.
• o Proposed a novel algorithm to downsize standard cells and reclaim area based on PT-SI timing without hurting setup and max transition. Implemented in an efficient TCL code.

Oct 2006 – Feb 2008 · 1 yr 4 mos · Giheung, South Korea

• Responsible for design methodology savvy implementation (Magma based) and Sign-Off of ASIC’s as part of Design Methodology Validation group. Also, learnt advanced design methodologies, viz. Flip Chip, Power Gating, Multi-Vdd and Additive Bulk Bias.

Dec 2003 – Sep 2006 · 2 yrs 9 mos · Greater Noida, India

• Design Engineer for set-top box SoCs. Responsible for Top level STA (PrimeTime), Integration and Updation of IPs (Clock Generator, DFT Controller, Memory Controller), Logic Synthesis and Equivalence Checking.