Monica R — Product Manager

I’m a VLSI Physical Design Engineer with 5+ years of hands-on experience driving SoC implementation and sign-off across advanced technology nodes (10nm → 3nm). My expertise spans synthesis, STA, IR/EM analysis, and low-power optimization, with a strong record of improving design efficiency and achieving robust PPA closure. Currently working at Samsung Semiconductor India Research (SSIR), I lead block-level physical implementation, top-level CLP sign-off, and automation initiatives using TCL and Python to streamline ECO and design quality workflows. Previously at MediaTek, Qualcomm, and Intel, I have contributed to multiple multi-power domain and top-level SoC projects, successfully reducing leakage power by 3% through innovative design methodologies. I’m passionate about scalable automation, low-power design strategies, and cross-functional collaboration that drives next-gen semiconductor innovation. 📍Open to global opportunities in Physical Design / STA / Synthesis, particularly in the UK or Europe under visa sponsorship. Let’s connect and collaborate on building high-performance, energy-efficient chips for the future

Stackforce AI infers this person is a VLSI Physical Design Engineer with a focus on low-power semiconductor solutions.

Location: Bengaluru, Karnataka, India

Experience: 6 yrs 6 mos