Sabarish Sree M

Software Engineer

Bengaluru, Karnataka, India9 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced SoC Design Engineer at Intel Corporation.
Strong expertise in Power Distribution and Design Rule Checking.
MTech in VLSI Design with hands-on experience in Physical Design.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in semiconductor design and physical design methodologies.

Contact

Skills

Core Skills

Power DistributionDesign Rule Checking (drc)Timing Closure

Other Skills

TimingStatic Timing AnalysisP&RFloorplanningCC++ProgrammingMicrosoft OfficeTeamwork8051 MicrocontrollerVerilogPerlTCLMicrosoft PowerPointPhysical Design

Experience

9 yrs

Total Experience

3 yrs

Average Tenure

7 yrs

Current Experience

Intel corporation

SoC Design Engineer

May 2019 – Present · 7 yrs · Bengaluru, Karnataka, India

Power DistributionDesign Rule Checking (DRC)

Mediatek

2 roles

Physical Design Engineer

Jul 2018 – May 2019 · 10 mos

Power DistributionDesign Rule Checking (DRC)

Intern

Jul 2017 – Jun 2018 · 11 mos

Power DistributionTiming Closure

Mu sigma

Trainee Decision Scientist

Jul 2014 – Oct 2014 · 3 mos

Education

Vellore Institute of Technology

Master of Technology (MTech) — Vlsi design

Jan 2016 – Jan 2018

Amrita School of Engineering Bangalore

Bachelor of Technology (BTech) — Electronics and Communications Engineering

Jan 2010 – Jan 2014

Kendriya Vidyalaya

11th

Jan 2008 – Jan 2010

Kendriya Vidyalaya

High School

Jan 2005 – Jan 2008

Stackforce found 100+ more professionals with Power Distribution & Design Rule Checking (drc)

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