Manish Agrawal

Software Engineer

Rajasthan, India8 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and Static Timing Analysis.
Led backend implementation for Cortex A53 CPU.
Strong background in Electronics industry with advanced tool expertise.

Stackforce AI infers this person is a Backend Physical Design Engineer in the Electronics industry.

Contact

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Logic SynthesisPlace & RouteCadenceSynopsys toolsPnRSTALow power PnR implementationInnovusClock Tree SynthesisLayout Versus Schematic (LVS)Design Rule Checking (DRC)TCLSynopsys PrimetimeFloorplanningTiming Closure

About

Experienced Backend Physical Design Engineer with a demonstrated history of working in the Electronics industry. Skilled Synopsys and Cadence tools primary focus being in PnR and STA. Strong engineering professional with a Bachelor of Engineering - BE focused in Electronics and Instrumentation from Birla Institute of Technology and Science, Pilani.

Experience

8 yrs 3 mos

Total Experience

2 yrs 9 mos

Average Tenure

4 yrs 10 mos

Current Experience

Google

Silicon Engineer

Jun 2021 – Present · 4 yrs 10 mos · Bengaluru, Karnataka, India

Static Timing AnalysisLogic SynthesisPlace & RoutePhysical DesignCadenceSynopsys tools

Samsung r&d institute india - bangalore private limited

Associate staff engineer

Jun 2018 – Jun 2021 · 3 yrs · Bangalore

> Part of arm cores teams, with experience in latest samsung tech nodes and knowledge on complete backend flow , primary focusing on PnR , synthesis and sta.
> Owned complete backend implementation for Cortex A53 wrapper (Dual core)
> PnR implementation ownership of Cortex A53 CPU , Cortex R52 CPU and wrapper
> QoR enhancement trials for DSP and other blocks.
> STA ownership for CA53 cpu , CA76 , CA78 wrappers.

Place & RouteStatic Timing AnalysisLogic SynthesisPnRSTAPhysical Design