Naresh Lekkala

Software Engineer

Bengaluru, Karnataka, India10 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Senior Engineer with extensive experience in logic synthesis.
  • Expert in static timing analysis and digital logic design.
  • Strong background in low power analysis and signoff.
Stackforce AI infers this person is a VLSI design expert with a focus on digital logic and synthesis.

Contact

LinkedIn

Skills

Core Skills

Logic SynthesisStatic Timing Analysis

Other Skills

Physical SynthesisDigital logic designLow power analysis and signoffTiming SignoffPerl scriptingTCL scripting

Experience

10 yrs 11 mos
Total Experience
3 yrs 7 mos
Average Tenure
5 yrs
Current Experience

Qualcomm

Senior Engineer

May 2021 – Present · 5 yrs · Bengaluru, Karnataka, India · On-site

Logic SynthesisPhysical SynthesisStatic Timing AnalysisDigital logic designLow power analysis and signoffTiming Signoff+2

Mediatek

2 roles

Senior Engineer

Promoted

Jul 2019 – Apr 2021 · 1 yr 9 mos · Bangalore Urban, Karnataka, India

Engineer

Jul 2017 – Jul 2019 · 2 yrs · Bangalore Urban, Karnataka, India

  • Currently working as Synthesis and STA Engineer

Unisys global services india

Technical Associate

Apr 2013 – Jun 2015 · 2 yrs 2 mos

Education

International Institute of Information Technology Bangalore

Master's degree — System on Chip (VLSI)

Jan 2015 – Jan 2017

Chaitanya Engineering College

B.Tech — Electronics and Communications Engineering

Jan 2008 – Jan 2012

Stackforce found 100+ more professionals with Logic Synthesis & Static Timing Analysis

Explore similar profiles based on matching skills and experience

MR

Monica R

Staff Associate

at Samsung Semiconductor

Bengaluru, India6 yrs 6 mos exp
Physical DesignLow-power Design
Hema Lakshmi Singana

Hema Lakshmi Singana

Synthesis Engineer

at MediaTek

Bengaluru, India5 yrs 5 mos exp
Physical DesignSynthesis
ravneet singh

ravneet singh

Director

at Samsung Electronics

Bengaluru, India21 yrs 8 mos exp
SoCASICPhysical DesignVLSI
Mallina Rajesh

Mallina Rajesh

Senior Design Engineer

at AMD

Bengaluru, India18 yrs 8 mos exp
VLSIPhysical DesignTiming Closure
Vikas Verma

Vikas Verma

Senior Staff Engineer

at MediaTek

Bengaluru, India13 yrs 6 mos exp
VLSISoCPhysical DesignTiming Closure
Deeksha Tiwari

Deeksha Tiwari

SoC Design Intern

at Intel Corporation

Gurgaon, India0 mo exp
VLSI Physical Design
Himanshu Gupta

Himanshu Gupta

Digital Design Engineer

at Intel Corporation

Lucknow, India1 yr 9 mos exp
Digital Circuit DesignVLSI
NK

Nikhil Khandelwal

Principal Engineer

at Arm

Noida, India15 yrs 7 mos exp
ASICPhysical Design